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文件名称:CHENLI_VHDL_FINAL

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [HTML]
  • 上传时间：
    2013-04-08
  • 文件大小：
    395.08kb
  • 已下载：
    0次
  • 提 供 者：
    Li ****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

四个按钮代表加法，减法，乘法和输入。也有8个二进制开关，用于输入两个操作数为每个计算。四位十六进制显示所选择的操作数和计算结果。-You will design a hexadecimal calculator.four push buttons represent Addition, Subtraction, Multiplication and Enter. There are also eight binary switches used to enter two operands for each calculation. The four digit hexadecimal display shows the selected operands and the calculated result.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

CHENLI_VHDL_FINAL/
CHENLI_VHDL_FINAL/calculate.vhd
CHENLI_VHDL_FINAL/calculator_topdesign.bgn
CHENLI_VHDL_FINAL/calculator_topdesign.bit
CHENLI_VHDL_FINAL/Calculator_TopDesign.bld
CHENLI_VHDL_FINAL/Calculator_TopDesign.cmd_log
CHENLI_VHDL_FINAL/calculator_topdesign.drc
CHENLI_VHDL_FINAL/Calculator_TopDesign.lso
CHENLI_VHDL_FINAL/Calculator_TopDesign.ncd
CHENLI_VHDL_FINAL/Calculator_TopDesign.ngc
CHENLI_VHDL_FINAL/Calculator_TopDesign.ngd
CHENLI_VHDL_FINAL/Calculator_TopDesign.ngr
CHENLI_VHDL_FINAL/Calculator_TopDesign.pad
CHENLI_VHDL_FINAL/Calculator_TopDesign.par
CHENLI_VHDL_FINAL/Calculator_TopDesign.pcf
CHENLI_VHDL_FINAL/Calculator_TopDesign.prj
CHENLI_VHDL_FINAL/Calculator_TopDesign.ptwx
CHENLI_VHDL_FINAL/Calculator_TopDesign.stx
CHENLI_VHDL_FINAL/Calculator_TopDesign.syr
CHENLI_VHDL_FINAL/Calculator_TopDesign.twr
CHENLI_VHDL_FINAL/Calculator_TopDesign.twx
CHENLI_VHDL_FINAL/Calculator_TopDesign.unroutes
CHENLI_VHDL_FINAL/Calculator_TopDesign.ut
CHENLI_VHDL_FINAL/Calculator_TopDesign.vhd
CHENLI_VHDL_FINAL/Calculator_TopDesign.xpi
CHENLI_VHDL_FINAL/Calculator_TopDesign.xst
CHENLI_VHDL_FINAL/Calculator_TopDesign_guide.ncd
CHENLI_VHDL_FINAL/Calculator_TopDesign_map.map
CHENLI_VHDL_FINAL/Calculator_TopDesign_map.mrp
CHENLI_VHDL_FINAL/Calculator_TopDesign_map.ncd
CHENLI_VHDL_FINAL/Calculator_TopDesign_map.ngm
CHENLI_VHDL_FINAL/Calculator_TopDesign_map.xrpt
CHENLI_VHDL_FINAL/Calculator_TopDesign_ngdbuild.xrpt
CHENLI_VHDL_FINAL/Calculator_TopDesign_pad.csv
CHENLI_VHDL_FINAL/Calculator_TopDesign_pad.txt
CHENLI_VHDL_FINAL/Calculator_TopDesign_par.xrpt
CHENLI_VHDL_FINAL/Calculator_TopDesign_prev_built.ngd
CHENLI_VHDL_FINAL/Calculator_TopDesign_summary.html
CHENLI_VHDL_FINAL/Calculator_TopDesign_summary.xml
CHENLI_VHDL_FINAL/Calculator_TopDesign_usage.xml
CHENLI_VHDL_FINAL/Calculator_TopDesign_vhdl.prj
CHENLI_VHDL_FINAL/Calculator_TopDesign_xst.xrpt
CHENLI_VHDL_FINAL/CHENLI_VHDL.gise
CHENLI_VHDL_FINAL/CHENLI_VHDL.ise
CHENLI_VHDL_FINAL/CHENLI_VHDL.ntrc_log
CHENLI_VHDL_FINAL/CHENLI_VHDL.xise
CHENLI_VHDL_FINAL/CHENLI_VHDL_xdb/
CHENLI_VHDL_FINAL/CHENLI_VHDL_xdb/cst.xbcd
CHENLI_VHDL_FINAL/CHENLI_VHDL_xdb/tmp/
CHENLI_VHDL_FINAL/CHENLI_VHDL_xdb/tmp/ise/
CHENLI_VHDL_FINAL/CHENLI_VHDL_xdb/tmp/ise.lock
CHENLI_VHDL_FINAL/CHENLI_VHDL_xdb/tmp/ise/version
CHENLI_VHDL_FINAL/CHENLI_VHDL_xdb/tmp/ise/__OBJSTORE__/
CHENLI_VHDL_FINAL/CHENLI_VHDL_xdb/tmp/ise/__OBJSTORE__/Autonym/
CHENLI_VHDL_FINAL/CHENLI_VHDL_xdb/tmp/ise/__OBJSTORE__/common/
CHENLI_VHDL_FINAL/CHENLI_VHDL_xdb/tmp/ise/__OBJSTORE__/HierarchicalDesign/
CHENLI_VHDL_FINAL/CHENLI_VHDL_xdb/tmp/ise/__OBJSTORE__/HierarchicalDesign/HDProject/
CHENLI_VHDL_FINAL/CHENLI_VHDL_xdb/tmp/ise/__OBJSTORE__/HierarchicalDesign/HDProject/HDProject
CHENLI_VHDL_FINAL/CHENLI_VHDL_xdb/tmp/ise/__OBJSTORE__/HierarchicalDesign/HDProject/HDProject_StrTbl
CHENLI_VHDL_FINAL/CHENLI_VHDL_xdb/tmp/ise/__OBJSTORE__/HierarchicalDesign/__stored_object_table__
CHENLI_VHDL_FINAL/CHENLI_VHDL_xdb/tmp/ise/__OBJSTORE__/PnAutoRun/
CHENLI_VHDL_FINAL/CHENLI_VHDL_xdb/tmp/ise/__OBJSTORE__/PnAutoRun/Scripts/
CHENLI_VHDL_FINAL/CHENLI_VHDL_xdb/tmp/ise/__OBJSTORE__/PnAutoRun/Scripts/RunOnce_tcl
CHENLI_VHDL_FINAL/CHENLI_VHDL_xdb/tmp/ise/__OBJSTORE__/PnAutoRun/Scripts/RunOnce_tcl_StrTbl
CHENLI_VHDL_FINAL/CHENLI_VHDL_xdb/tmp/ise/__OBJSTORE__/ProjectNavigator/
CHENLI_VHDL_FINAL/CHENLI_VHDL_xdb/tmp/ise/__OBJSTORE__/ProjectNavigator11/
CHENLI_VHDL_FINAL/CHENLI_VHDL_xdb/tmp/ise/__OBJSTORE__/ProjectNavigatorGui/
CHENLI_VHDL_FINAL/CHENLI_VHDL_xdb/tmp/ise/__OBJSTORE__/ProjectNavigatorGui/CViewSelector
CHENLI_VHDL_FINAL/CHENLI_VHDL_xdb/tmp/ise/__OBJSTORE__/ProjectNavigatorGui/CViewSelector_StrTbl
CHENLI_VHDL_FINAL/CHENLI_VHDL_xdb/tmp/ise/__OBJSTORE__/ProjectNavigatorGui/File-SynthesisOnly
CHENLI_VHDL_FINAL/CHENLI_VHDL_xdb/tmp/ise/__OBJSTORE__/ProjectNavigatorGui/File-SynthesisOnly_StrTbl
CHENLI_VHDL_FINAL/CHENLI_VHDL_xdb/tmp/ise/__OBJSTORE__/ProjectNavigatorGui/Library-SynthesisOnly
CHENLI_VHDL_FINAL/CHENLI_VHDL_xdb/tmp/ise/__OBJSTORE__/ProjectNavigatorGui/Library-SynthesisOnly_StrTbl
CHENLI_VHDL_FINAL/CHENLI_VHDL_xdb/tmp/ise/__OBJSTORE__/ProjectNavigatorGui/Process-SynthesisOnly-
CHENLI_VHDL_FINAL/CHENLI_VHDL_xdb/tmp/ise/__OBJSTORE__/ProjectNavigatorGui/Process-SynthesisOnly-DESUT_VHDL_ARCHITECTURE
CHENLI_VHDL_FINAL/CHENLI_VHDL_xdb/tmp/ise/__OBJSTORE__/ProjectNavigatorGui/Process-SynthesisOnly-DESUT_VHDL_ARCHITECTURE_StrTbl
CHENLI_VHDL_FINAL/CHENLI_VHDL_xdb/tmp/ise/__OBJSTORE__/ProjectNavigatorGui/Process-SynthesisOnly-_StrTbl
CHENLI_VHDL_FINAL/CHENLI_VHDL_xdb/tmp/ise/__OBJSTORE__/ProjectNavigatorGui/Source-SynthesisOnly-AutoCompile
CHENLI_VHDL_FINAL/CHENLI_VHDL_xdb/tmp/ise/__OBJSTORE__/ProjectNavigatorGui/Source-SynthesisOnly-AutoCompile_StrTbl
CHENLI_VHDL_FINAL/CHENLI_VHDL_xdb/tmp/ise/__OBJSTORE__/ProjectNavigator/dpm_project_main/
CHENLI_VHDL_FINAL/CHENLI_VHDL_xdb/tmp/ise/__OBJSTORE__/ProjectNavigator/dpm_project_main/dpm_project_main
CHENLI_VHDL_FINAL/CHENLI_VHDL_xdb/tmp/ise/__OBJSTORE__/ProjectNavigator/dpm_project_main/dpm_project_main_StrTbl
CHENLI_VHDL_FINAL/CHENLI_VHDL_xdb/tmp/ise/__OBJSTORE__/WebTalk/
CHENLI_VHDL_FINAL/CHENLI_VHDL_xdb/tmp/is

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