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文件名称:mb
介绍说明--下载内容来自于网络,使用问题请自行百度
基于Proasic3 startkit 开发板,用verilog语言描述的一个秒表计数器。-Based the ProASIC3 StartKit development board, using Verilog language descr iption of a stopwatch counter.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
mb/designer/impl1/designer.log
mb/designer/impl1/designer_genhdl.log
mb/designer/impl1/simulation/postlayout/top/verilog.psm
mb/designer/impl1/simulation/postlayout/top/_primary.dat
mb/designer/impl1/simulation/postlayout/top/_primary.dbs
mb/designer/impl1/simulation/postlayout/top/_primary.vhd
mb/designer/impl1/simulation/postlayout/_info
mb/designer/impl1/top.adb
mb/designer/impl1/top.dtf/verify.log
mb/designer/impl1/top.ide_des
mb/designer/impl1/top.pdb
mb/designer/impl1/top.pdb.depends
mb/designer/impl1/top.tcl
mb/designer/impl1/top_1.adb
mb/designer/impl1/top_1.dtf/verify.log
mb/designer/impl1/top_1.ide_des
mb/designer/impl1/top_1.pdb
mb/designer/impl1/top_1.pdb.depends
mb/designer/impl1/top_1_ba.sdf
mb/designer/impl1/top_1_ba.v
mb/designer/impl1/top_1_fp/$$FlashPro_09003.L$$
mb/designer/impl1/top_1_fp/projectData/top_1.pdb
mb/designer/impl1/top_1_fp/top_1.log
mb/designer/impl1/top_1_fp/top_1.pro
mb/designer/impl1/top_2.adb
mb/designer/impl1/top_2.dtf/verify.log
mb/designer/impl1/top_2.ide_des
mb/designer/impl1/top_2.pdb
mb/designer/impl1/top_2.pdb.depends
mb/designer/impl1/top_2_ba.sdf
mb/designer/impl1/top_2_ba.v
mb/designer/impl1/top_2_fp/$$FlashPro_09003.L$$
mb/designer/impl1/top_2_fp/projectData/top_2.pdb
mb/designer/impl1/top_2_fp/top_2.log
mb/designer/impl1/top_2_fp/top_2.pro
mb/designer/impl1/top_3.adb
mb/designer/impl1/top_3.dtf/verify.log
mb/designer/impl1/top_3.ide_des
mb/designer/impl1/top_3.pdb
mb/designer/impl1/top_3.pdb.depends
mb/designer/impl1/top_3_ba.sdf
mb/designer/impl1/top_3_ba.v
mb/designer/impl1/top_3_fp/$$FlashPro_09003.L$$
mb/designer/impl1/top_3_fp/projectData/top_3.pdb
mb/designer/impl1/top_3_fp/top_3.log
mb/designer/impl1/top_3_fp/top_3.pro
mb/designer/impl1/top_ba.sdf
mb/designer/impl1/top_ba.v
mb/designer/impl1/top_fp/$$FlashPro_09003.L$$
mb/designer/impl1/top_fp/projectData/top.pdb
mb/designer/impl1/top_fp/top.log
mb/designer/impl1/top_fp/top.pro
mb/hdl/js.v
mb/hdl/latch.v
mb/hdl/top.v
mb/mb.prj
mb/simulation/modelsim.ini
mb/simulation/modelsim.ini.sav
mb/simulation/modelsim.log
mb/simulation/postsynth/display/verilog.psm
mb/simulation/postsynth/display/_primary.dat
mb/simulation/postsynth/display/_primary.dbs
mb/simulation/postsynth/display/_primary.vhd
mb/simulation/postsynth/js/verilog.psm
mb/simulation/postsynth/js/_primary.dat
mb/simulation/postsynth/js/_primary.dbs
mb/simulation/postsynth/js/_primary.vhd
mb/simulation/postsynth/latch/verilog.psm
mb/simulation/postsynth/latch/_primary.dat
mb/simulation/postsynth/latch/_primary.dbs
mb/simulation/postsynth/latch/_primary.vhd
mb/simulation/postsynth/top/verilog.psm
mb/simulation/postsynth/top/_primary.dat
mb/simulation/postsynth/top/_primary.dbs
mb/simulation/postsynth/top/_primary.vhd
mb/simulation/postsynth/_info
mb/simulation/presynth/js/verilog.psm
mb/simulation/presynth/js/_primary.dat
mb/simulation/presynth/js/_primary.dbs
mb/simulation/presynth/js/_primary.vhd
mb/simulation/presynth/latch/verilog.psm
mb/simulation/presynth/latch/_primary.dat
mb/simulation/presynth/latch/_primary.dbs
mb/simulation/presynth/latch/_primary.vhd
mb/simulation/presynth/top/verilog.psm
mb/simulation/presynth/top/_primary.dat
mb/simulation/presynth/top/_primary.dbs
mb/simulation/presynth/top/_primary.vhd
mb/simulation/presynth/_info
mb/simulation/run.do
mb/simulation/vsim.wlf
mb/simulation/work/display/verilog.psm
mb/simulation/work/display/_primary.dat
mb/simulation/work/display/_primary.dbs
mb/simulation/work/display/_primary.vhd
mb/simulation/work/js/verilog.psm
mb/simulation/work/js/_primary.dat
mb/simulation/work/js/_primary.dbs
mb/simulation/work/js/_primary.vhd
mb/simulation/work/latch/verilog.psm
mb/simulation/work/latch/_primary.dat
mb/simulation/work/latch/_primary.dbs
mb/simulation/work/latch/_primary.vhd
mb/simulation/work/top/verilog.psm
mb/simulation/work/top/_primary.dat
mb/simulation/work/top/_primary.dbs
mb/simulation/work/top/_primary.vhd
mb/simulation/work/_info
mb/smartgen/smartgen.aws
mb/synthesis/.recordref
mb/synthesis/backup/top.srr
mb/synthesis/backup/top_1.srr
mb/synthesis/backup/top_2.srr
mb/synthesis/backup/top_3.srr
mb/synthesis/run_options.txt
mb/synthesis/stdout.log
mb/synthesis/syntmp/sap.log
mb/synthesis/syntmp/top.msg
mb/synthesis/syntmp/top.plg
mb/synthesis/syntmp/top_1.msg
mb/synthesis/syntmp/top_1.plg
mb/synthesis/syntmp/top_1_flink.htm
mb/synthesis/syntmp/top_1_srr.htm
mb/synthesis/syntmp/top_1_toc.htm
mb/synthesis/syntmp/top_2.msg
mb/synthesis/syntmp/top_2.plg
mb/synthesis/syntmp/top_2_flink.htm
mb/synthesis/syntmp/top_2_srr.htm
mb/synthesis/syntmp/top_2_toc.htm
mb/synthesis/syntmp/top_3.msg
mb/synthesis/syntmp/top_3.plg
mb/synthesis/syntmp/top_3_flink.htm
mb/synthesis/syntmp/top_3_srr.htm
mb/synthesis/syntmp/top_3_toc.htm
mb/synthesis/syntmp/top_flink.htm
mb/synthesis/syntmp/top_srr.htm
mb/synthesis/syntmp/top_toc.htm
mb/synthesis/top.areasrr
mb/synthesis/top.edn
mb/synthesis/top.fse
mb/synthesis/top.htm
mb/synthesis/top.map
mb/synthesis/top.sap
mb/synthesis/top.sdf
mb/synthesis/top.so
mb/synthesis/top.srd
mb/synthesis/top.srm
mb/synthesis/top.srr
mb/synthesis/top.srs
mb/synthesis/top.tlg
mb/synthesis/top.v
mb/synt
mb/designer/impl1/designer_genhdl.log
mb/designer/impl1/simulation/postlayout/top/verilog.psm
mb/designer/impl1/simulation/postlayout/top/_primary.dat
mb/designer/impl1/simulation/postlayout/top/_primary.dbs
mb/designer/impl1/simulation/postlayout/top/_primary.vhd
mb/designer/impl1/simulation/postlayout/_info
mb/designer/impl1/top.adb
mb/designer/impl1/top.dtf/verify.log
mb/designer/impl1/top.ide_des
mb/designer/impl1/top.pdb
mb/designer/impl1/top.pdb.depends
mb/designer/impl1/top.tcl
mb/designer/impl1/top_1.adb
mb/designer/impl1/top_1.dtf/verify.log
mb/designer/impl1/top_1.ide_des
mb/designer/impl1/top_1.pdb
mb/designer/impl1/top_1.pdb.depends
mb/designer/impl1/top_1_ba.sdf
mb/designer/impl1/top_1_ba.v
mb/designer/impl1/top_1_fp/$$FlashPro_09003.L$$
mb/designer/impl1/top_1_fp/projectData/top_1.pdb
mb/designer/impl1/top_1_fp/top_1.log
mb/designer/impl1/top_1_fp/top_1.pro
mb/designer/impl1/top_2.adb
mb/designer/impl1/top_2.dtf/verify.log
mb/designer/impl1/top_2.ide_des
mb/designer/impl1/top_2.pdb
mb/designer/impl1/top_2.pdb.depends
mb/designer/impl1/top_2_ba.sdf
mb/designer/impl1/top_2_ba.v
mb/designer/impl1/top_2_fp/$$FlashPro_09003.L$$
mb/designer/impl1/top_2_fp/projectData/top_2.pdb
mb/designer/impl1/top_2_fp/top_2.log
mb/designer/impl1/top_2_fp/top_2.pro
mb/designer/impl1/top_3.adb
mb/designer/impl1/top_3.dtf/verify.log
mb/designer/impl1/top_3.ide_des
mb/designer/impl1/top_3.pdb
mb/designer/impl1/top_3.pdb.depends
mb/designer/impl1/top_3_ba.sdf
mb/designer/impl1/top_3_ba.v
mb/designer/impl1/top_3_fp/$$FlashPro_09003.L$$
mb/designer/impl1/top_3_fp/projectData/top_3.pdb
mb/designer/impl1/top_3_fp/top_3.log
mb/designer/impl1/top_3_fp/top_3.pro
mb/designer/impl1/top_ba.sdf
mb/designer/impl1/top_ba.v
mb/designer/impl1/top_fp/$$FlashPro_09003.L$$
mb/designer/impl1/top_fp/projectData/top.pdb
mb/designer/impl1/top_fp/top.log
mb/designer/impl1/top_fp/top.pro
mb/hdl/js.v
mb/hdl/latch.v
mb/hdl/top.v
mb/mb.prj
mb/simulation/modelsim.ini
mb/simulation/modelsim.ini.sav
mb/simulation/modelsim.log
mb/simulation/postsynth/display/verilog.psm
mb/simulation/postsynth/display/_primary.dat
mb/simulation/postsynth/display/_primary.dbs
mb/simulation/postsynth/display/_primary.vhd
mb/simulation/postsynth/js/verilog.psm
mb/simulation/postsynth/js/_primary.dat
mb/simulation/postsynth/js/_primary.dbs
mb/simulation/postsynth/js/_primary.vhd
mb/simulation/postsynth/latch/verilog.psm
mb/simulation/postsynth/latch/_primary.dat
mb/simulation/postsynth/latch/_primary.dbs
mb/simulation/postsynth/latch/_primary.vhd
mb/simulation/postsynth/top/verilog.psm
mb/simulation/postsynth/top/_primary.dat
mb/simulation/postsynth/top/_primary.dbs
mb/simulation/postsynth/top/_primary.vhd
mb/simulation/postsynth/_info
mb/simulation/presynth/js/verilog.psm
mb/simulation/presynth/js/_primary.dat
mb/simulation/presynth/js/_primary.dbs
mb/simulation/presynth/js/_primary.vhd
mb/simulation/presynth/latch/verilog.psm
mb/simulation/presynth/latch/_primary.dat
mb/simulation/presynth/latch/_primary.dbs
mb/simulation/presynth/latch/_primary.vhd
mb/simulation/presynth/top/verilog.psm
mb/simulation/presynth/top/_primary.dat
mb/simulation/presynth/top/_primary.dbs
mb/simulation/presynth/top/_primary.vhd
mb/simulation/presynth/_info
mb/simulation/run.do
mb/simulation/vsim.wlf
mb/simulation/work/display/verilog.psm
mb/simulation/work/display/_primary.dat
mb/simulation/work/display/_primary.dbs
mb/simulation/work/display/_primary.vhd
mb/simulation/work/js/verilog.psm
mb/simulation/work/js/_primary.dat
mb/simulation/work/js/_primary.dbs
mb/simulation/work/js/_primary.vhd
mb/simulation/work/latch/verilog.psm
mb/simulation/work/latch/_primary.dat
mb/simulation/work/latch/_primary.dbs
mb/simulation/work/latch/_primary.vhd
mb/simulation/work/top/verilog.psm
mb/simulation/work/top/_primary.dat
mb/simulation/work/top/_primary.dbs
mb/simulation/work/top/_primary.vhd
mb/simulation/work/_info
mb/smartgen/smartgen.aws
mb/synthesis/.recordref
mb/synthesis/backup/top.srr
mb/synthesis/backup/top_1.srr
mb/synthesis/backup/top_2.srr
mb/synthesis/backup/top_3.srr
mb/synthesis/run_options.txt
mb/synthesis/stdout.log
mb/synthesis/syntmp/sap.log
mb/synthesis/syntmp/top.msg
mb/synthesis/syntmp/top.plg
mb/synthesis/syntmp/top_1.msg
mb/synthesis/syntmp/top_1.plg
mb/synthesis/syntmp/top_1_flink.htm
mb/synthesis/syntmp/top_1_srr.htm
mb/synthesis/syntmp/top_1_toc.htm
mb/synthesis/syntmp/top_2.msg
mb/synthesis/syntmp/top_2.plg
mb/synthesis/syntmp/top_2_flink.htm
mb/synthesis/syntmp/top_2_srr.htm
mb/synthesis/syntmp/top_2_toc.htm
mb/synthesis/syntmp/top_3.msg
mb/synthesis/syntmp/top_3.plg
mb/synthesis/syntmp/top_3_flink.htm
mb/synthesis/syntmp/top_3_srr.htm
mb/synthesis/syntmp/top_3_toc.htm
mb/synthesis/syntmp/top_flink.htm
mb/synthesis/syntmp/top_srr.htm
mb/synthesis/syntmp/top_toc.htm
mb/synthesis/top.areasrr
mb/synthesis/top.edn
mb/synthesis/top.fse
mb/synthesis/top.htm
mb/synthesis/top.map
mb/synthesis/top.sap
mb/synthesis/top.sdf
mb/synthesis/top.so
mb/synthesis/top.srd
mb/synthesis/top.srm
mb/synthesis/top.srr
mb/synthesis/top.srs
mb/synthesis/top.tlg
mb/synthesis/top.v
mb/synt
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