文件名称:EX3
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- 上传时间:2013-07-10
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文件大小:436.25kb
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已下载:0次
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介绍说明--下载内容来自于网络,使用问题请自行百度
基于FPGA的数码管显示,给刚入门的朋友-FPGA-based digital display, to see friends just getting started. .
(系统自动生成,下载前可以参看下载内容)
下载文件列表
EX3/db/LED_SEG7_2.(0).cnf.cdb
EX3/db/LED_SEG7_2.(0).cnf.hdb
EX3/db/LED_SEG7_2.asm.qmsg
EX3/db/LED_SEG7_2.asm.rdb
EX3/db/LED_SEG7_2.asm_labs.ddb
EX3/db/LED_SEG7_2.atom_map.rvd
EX3/db/LED_SEG7_2.cbx.xml
EX3/db/LED_SEG7_2.cmp.cdb
EX3/db/LED_SEG7_2.cmp.hdb
EX3/db/LED_SEG7_2.cmp.idb
EX3/db/LED_SEG7_2.cmp.kpt
EX3/db/LED_SEG7_2.cmp.logdb
EX3/db/LED_SEG7_2.cmp.rdb
EX3/db/LED_SEG7_2.cmp0.ddb
EX3/db/LED_SEG7_2.db_info
EX3/db/LED_SEG7_2.eda.qmsg
EX3/db/LED_SEG7_2.fit.qmsg
EX3/db/LED_SEG7_2.hier_info
EX3/db/LED_SEG7_2.hif
EX3/db/LED_SEG7_2.ipinfo
EX3/db/LED_SEG7_2.lpc.html
EX3/db/LED_SEG7_2.lpc.rdb
EX3/db/LED_SEG7_2.lpc.txt
EX3/db/LED_SEG7_2.map.cdb
EX3/db/LED_SEG7_2.map.hdb
EX3/db/LED_SEG7_2.map.logdb
EX3/db/LED_SEG7_2.map.qmsg
EX3/db/LED_SEG7_2.map.rdb
EX3/db/LED_SEG7_2.pplq.rdb
EX3/db/LED_SEG7_2.pre_map.cdb
EX3/db/LED_SEG7_2.pre_map.hdb
EX3/db/LED_SEG7_2.qns
EX3/db/LED_SEG7_2.root_partition.map.reg_db.cdb
EX3/db/LED_SEG7_2.routing.rdb
EX3/db/LED_SEG7_2.rpp.qmsg
EX3/db/LED_SEG7_2.rtlv.hdb
EX3/db/LED_SEG7_2.rtlv_sg.cdb
EX3/db/LED_SEG7_2.rtlv_sg_swap.cdb
EX3/db/LED_SEG7_2.sas
EX3/db/LED_SEG7_2.sgate.rvd
EX3/db/LED_SEG7_2.sgate_sm.rvd
EX3/db/LED_SEG7_2.sgdiff.cdb
EX3/db/LED_SEG7_2.sgdiff.hdb
EX3/db/LED_SEG7_2.sld_design_entry.sci
EX3/db/LED_SEG7_2.sld_design_entry_dsc.sci
EX3/db/LED_SEG7_2.smart_action.txt
EX3/db/LED_SEG7_2.sta.qmsg
EX3/db/LED_SEG7_2.sta.rdb
EX3/db/LED_SEG7_2.sta_cmp.5_slow.tdb
EX3/db/LED_SEG7_2.syn_hier_info
EX3/db/LED_SEG7_2.taw.rdb
EX3/db/LED_SEG7_2.tis_db_list.ddb
EX3/db/LED_SEG7_2.vpr.ammdb
EX3/db/logic_util_heursitic.dat
EX3/db/prev_cmp_LED_SEG7_2.qmsg
EX3/incremental_db/compiled_partitions/LED_SEG7_2.db_info
EX3/incremental_db/compiled_partitions/LED_SEG7_2.root_partition.map.kpt
EX3/incremental_db/README
EX3/LED_SEG7_2.jdi
EX3/LED_SEG7_2.qpf
EX3/LED_SEG7_2.qsf
EX3/LED_SEG7_2.qws
EX3/LED_SEG7_2.sdc
EX3/LED_SEG7_2.v
EX3/LED_SEG7_2.v.bak
EX3/LED_SEG7_2_nativelink_simulation.rpt
EX3/output_files/LED_SEG7_2.asm.rpt
EX3/output_files/LED_SEG7_2.done
EX3/output_files/LED_SEG7_2.eda.rpt
EX3/output_files/LED_SEG7_2.fit.rpt
EX3/output_files/LED_SEG7_2.fit.smsg
EX3/output_files/LED_SEG7_2.fit.summary
EX3/output_files/LED_SEG7_2.flow.rpt
EX3/output_files/LED_SEG7_2.jdi
EX3/output_files/LED_SEG7_2.map.rpt
EX3/output_files/LED_SEG7_2.map.summary
EX3/output_files/LED_SEG7_2.pin
EX3/output_files/LED_SEG7_2.pof
EX3/output_files/LED_SEG7_2.sta.rpt
EX3/output_files/LED_SEG7_2.sta.summary
EX3/simulation/modelsim/LED_SEG7_2.sft
EX3/simulation/modelsim/LED_SEG7_2.vo
EX3/simulation/modelsim/LED_SEG7_2.vt
EX3/simulation/modelsim/LED_SEG7_2.vt.bak
EX3/simulation/modelsim/LED_SEG7_2_modelsim.xrf
EX3/simulation/modelsim/LED_SEG7_2_run_msim_rtl_verilog.do
EX3/simulation/modelsim/LED_SEG7_2_run_msim_rtl_verilog.do.bak
EX3/simulation/modelsim/LED_SEG7_2_run_msim_rtl_verilog.do.bak1
EX3/simulation/modelsim/LED_SEG7_2_run_msim_rtl_verilog.do.bak2
EX3/simulation/modelsim/LED_SEG7_2_run_msim_rtl_verilog.do.bak3
EX3/simulation/modelsim/LED_SEG7_2_run_msim_rtl_verilog.do.bak4
EX3/simulation/modelsim/LED_SEG7_2_v.sdo
EX3/simulation/modelsim/modelsim.ini
EX3/simulation/modelsim/msim_transcript
EX3/simulation/modelsim/rtl_work/@l@e@d_@s@e@g7_2/verilog.prw
EX3/simulation/modelsim/rtl_work/@l@e@d_@s@e@g7_2/verilog.psm
EX3/simulation/modelsim/rtl_work/@l@e@d_@s@e@g7_2/_primary.dat
EX3/simulation/modelsim/rtl_work/@l@e@d_@s@e@g7_2/_primary.dbs
EX3/simulation/modelsim/rtl_work/@l@e@d_@s@e@g7_2/_primary.vhd
EX3/simulation/modelsim/rtl_work/@l@e@d_@s@e@g7_2_vlg_tst/verilog.prw
EX3/simulation/modelsim/rtl_work/@l@e@d_@s@e@g7_2_vlg_tst/verilog.psm
EX3/simulation/modelsim/rtl_work/@l@e@d_@s@e@g7_2_vlg_tst/_primary.dat
EX3/simulation/modelsim/rtl_work/@l@e@d_@s@e@g7_2_vlg_tst/_primary.dbs
EX3/simulation/modelsim/rtl_work/@l@e@d_@s@e@g7_2_vlg_tst/_primary.vhd
EX3/simulation/modelsim/rtl_work/_info
EX3/simulation/modelsim/rtl_work/_vmake
EX3/simulation/modelsim/vish_stacktrace.vstf
EX3/simulation/modelsim/vsim.wlf
EX3/simulation/modelsim/rtl_work/@l@e@d_@s@e@g7_2
EX3/simulation/modelsim/rtl_work/@l@e@d_@s@e@g7_2_vlg_tst
EX3/simulation/modelsim/rtl_work/_temp
EX3/simulation/modelsim/rtl_work
EX3/incremental_db/compiled_partitions
EX3/simulation/modelsim
EX3/db
EX3/incremental_db
EX3/output_files
EX3/simulation
EX3
EX3/db/LED_SEG7_2.(0).cnf.hdb
EX3/db/LED_SEG7_2.asm.qmsg
EX3/db/LED_SEG7_2.asm.rdb
EX3/db/LED_SEG7_2.asm_labs.ddb
EX3/db/LED_SEG7_2.atom_map.rvd
EX3/db/LED_SEG7_2.cbx.xml
EX3/db/LED_SEG7_2.cmp.cdb
EX3/db/LED_SEG7_2.cmp.hdb
EX3/db/LED_SEG7_2.cmp.idb
EX3/db/LED_SEG7_2.cmp.kpt
EX3/db/LED_SEG7_2.cmp.logdb
EX3/db/LED_SEG7_2.cmp.rdb
EX3/db/LED_SEG7_2.cmp0.ddb
EX3/db/LED_SEG7_2.db_info
EX3/db/LED_SEG7_2.eda.qmsg
EX3/db/LED_SEG7_2.fit.qmsg
EX3/db/LED_SEG7_2.hier_info
EX3/db/LED_SEG7_2.hif
EX3/db/LED_SEG7_2.ipinfo
EX3/db/LED_SEG7_2.lpc.html
EX3/db/LED_SEG7_2.lpc.rdb
EX3/db/LED_SEG7_2.lpc.txt
EX3/db/LED_SEG7_2.map.cdb
EX3/db/LED_SEG7_2.map.hdb
EX3/db/LED_SEG7_2.map.logdb
EX3/db/LED_SEG7_2.map.qmsg
EX3/db/LED_SEG7_2.map.rdb
EX3/db/LED_SEG7_2.pplq.rdb
EX3/db/LED_SEG7_2.pre_map.cdb
EX3/db/LED_SEG7_2.pre_map.hdb
EX3/db/LED_SEG7_2.qns
EX3/db/LED_SEG7_2.root_partition.map.reg_db.cdb
EX3/db/LED_SEG7_2.routing.rdb
EX3/db/LED_SEG7_2.rpp.qmsg
EX3/db/LED_SEG7_2.rtlv.hdb
EX3/db/LED_SEG7_2.rtlv_sg.cdb
EX3/db/LED_SEG7_2.rtlv_sg_swap.cdb
EX3/db/LED_SEG7_2.sas
EX3/db/LED_SEG7_2.sgate.rvd
EX3/db/LED_SEG7_2.sgate_sm.rvd
EX3/db/LED_SEG7_2.sgdiff.cdb
EX3/db/LED_SEG7_2.sgdiff.hdb
EX3/db/LED_SEG7_2.sld_design_entry.sci
EX3/db/LED_SEG7_2.sld_design_entry_dsc.sci
EX3/db/LED_SEG7_2.smart_action.txt
EX3/db/LED_SEG7_2.sta.qmsg
EX3/db/LED_SEG7_2.sta.rdb
EX3/db/LED_SEG7_2.sta_cmp.5_slow.tdb
EX3/db/LED_SEG7_2.syn_hier_info
EX3/db/LED_SEG7_2.taw.rdb
EX3/db/LED_SEG7_2.tis_db_list.ddb
EX3/db/LED_SEG7_2.vpr.ammdb
EX3/db/logic_util_heursitic.dat
EX3/db/prev_cmp_LED_SEG7_2.qmsg
EX3/incremental_db/compiled_partitions/LED_SEG7_2.db_info
EX3/incremental_db/compiled_partitions/LED_SEG7_2.root_partition.map.kpt
EX3/incremental_db/README
EX3/LED_SEG7_2.jdi
EX3/LED_SEG7_2.qpf
EX3/LED_SEG7_2.qsf
EX3/LED_SEG7_2.qws
EX3/LED_SEG7_2.sdc
EX3/LED_SEG7_2.v
EX3/LED_SEG7_2.v.bak
EX3/LED_SEG7_2_nativelink_simulation.rpt
EX3/output_files/LED_SEG7_2.asm.rpt
EX3/output_files/LED_SEG7_2.done
EX3/output_files/LED_SEG7_2.eda.rpt
EX3/output_files/LED_SEG7_2.fit.rpt
EX3/output_files/LED_SEG7_2.fit.smsg
EX3/output_files/LED_SEG7_2.fit.summary
EX3/output_files/LED_SEG7_2.flow.rpt
EX3/output_files/LED_SEG7_2.jdi
EX3/output_files/LED_SEG7_2.map.rpt
EX3/output_files/LED_SEG7_2.map.summary
EX3/output_files/LED_SEG7_2.pin
EX3/output_files/LED_SEG7_2.pof
EX3/output_files/LED_SEG7_2.sta.rpt
EX3/output_files/LED_SEG7_2.sta.summary
EX3/simulation/modelsim/LED_SEG7_2.sft
EX3/simulation/modelsim/LED_SEG7_2.vo
EX3/simulation/modelsim/LED_SEG7_2.vt
EX3/simulation/modelsim/LED_SEG7_2.vt.bak
EX3/simulation/modelsim/LED_SEG7_2_modelsim.xrf
EX3/simulation/modelsim/LED_SEG7_2_run_msim_rtl_verilog.do
EX3/simulation/modelsim/LED_SEG7_2_run_msim_rtl_verilog.do.bak
EX3/simulation/modelsim/LED_SEG7_2_run_msim_rtl_verilog.do.bak1
EX3/simulation/modelsim/LED_SEG7_2_run_msim_rtl_verilog.do.bak2
EX3/simulation/modelsim/LED_SEG7_2_run_msim_rtl_verilog.do.bak3
EX3/simulation/modelsim/LED_SEG7_2_run_msim_rtl_verilog.do.bak4
EX3/simulation/modelsim/LED_SEG7_2_v.sdo
EX3/simulation/modelsim/modelsim.ini
EX3/simulation/modelsim/msim_transcript
EX3/simulation/modelsim/rtl_work/@l@e@d_@s@e@g7_2/verilog.prw
EX3/simulation/modelsim/rtl_work/@l@e@d_@s@e@g7_2/verilog.psm
EX3/simulation/modelsim/rtl_work/@l@e@d_@s@e@g7_2/_primary.dat
EX3/simulation/modelsim/rtl_work/@l@e@d_@s@e@g7_2/_primary.dbs
EX3/simulation/modelsim/rtl_work/@l@e@d_@s@e@g7_2/_primary.vhd
EX3/simulation/modelsim/rtl_work/@l@e@d_@s@e@g7_2_vlg_tst/verilog.prw
EX3/simulation/modelsim/rtl_work/@l@e@d_@s@e@g7_2_vlg_tst/verilog.psm
EX3/simulation/modelsim/rtl_work/@l@e@d_@s@e@g7_2_vlg_tst/_primary.dat
EX3/simulation/modelsim/rtl_work/@l@e@d_@s@e@g7_2_vlg_tst/_primary.dbs
EX3/simulation/modelsim/rtl_work/@l@e@d_@s@e@g7_2_vlg_tst/_primary.vhd
EX3/simulation/modelsim/rtl_work/_info
EX3/simulation/modelsim/rtl_work/_vmake
EX3/simulation/modelsim/vish_stacktrace.vstf
EX3/simulation/modelsim/vsim.wlf
EX3/simulation/modelsim/rtl_work/@l@e@d_@s@e@g7_2
EX3/simulation/modelsim/rtl_work/@l@e@d_@s@e@g7_2_vlg_tst
EX3/simulation/modelsim/rtl_work/_temp
EX3/simulation/modelsim/rtl_work
EX3/incremental_db/compiled_partitions
EX3/simulation/modelsim
EX3/db
EX3/incremental_db
EX3/output_files
EX3/simulation
EX3
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