文件名称:div_clk
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- 上传时间:2013-08-20
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文件大小:40.44kb
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verilog实现任意时钟分频,简单明了,打开modelsim-change directroy-do sim .do 即可-Achieve any clock divider, simple, open modelsim-change directroy-do sim. Do to
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下载文件列表
work/sim/modelsim.ini
work/sim/sim.do
work/sim/sim.do.bak
work/sim/vsim.wlf
work/sim/wave.do
work/sim/wave.do.wlf
work/sim/work/div_clk/verilog.asm
work/sim/work/div_clk/verilog.rw
work/sim/work/div_clk/_primary.dat
work/sim/work/div_clk/_primary.dbs
work/sim/work/div_clk/_primary.vhd
work/sim/work/tb_div_clk/verilog.asm
work/sim/work/tb_div_clk/verilog.rw
work/sim/work/tb_div_clk/_primary.dat
work/sim/work/tb_div_clk/_primary.dbs
work/sim/work/tb_div_clk/_primary.vhd
work/sim/work/_info
work/sim/work/_temp/vlog01ywqq
work/sim/work/_temp/vlog02r1rb
work/sim/work/_temp/vlog1s1c8d
work/sim/work/_temp/vlog2q5gtd
work/sim/work/_temp/vlog2qf01e
work/sim/work/_temp/vlog34h7wx
work/sim/work/_temp/vlog5zna2g
work/sim/work/_temp/vlog7hzvm4
work/sim/work/_temp/vlogb16mmk
work/sim/work/_temp/vlogbajaxd
work/sim/work/_temp/vlogi1i97x
work/sim/work/_temp/vlogjic357
work/sim/work/_temp/vlogk8ydvd
work/sim/work/_temp/vlogkhxk6v
work/sim/work/_temp/vlogmvs3z7
work/sim/work/_temp/vlogr362xv
work/sim/work/_temp/vlogrzc3x9
work/sim/work/_temp/vlogsq4ez4
work/sim/work/_temp/vlogwwnhtg
work/sim/work/_temp/vlogyib26n
work/sim/work/_vmake
work/src/div.V.bak
work/src/div_clk.V
work/tb/tb_div.v.bak
work/tb/tb_div_clk.v
work/tb/tb_div_clk.v.bak
work/sim/work/div_clk
work/sim/work/tb_div_clk
work/sim/work/_temp
work/sim/work
work/sim
work/src
work/tb
work
work/sim/sim.do
work/sim/sim.do.bak
work/sim/vsim.wlf
work/sim/wave.do
work/sim/wave.do.wlf
work/sim/work/div_clk/verilog.asm
work/sim/work/div_clk/verilog.rw
work/sim/work/div_clk/_primary.dat
work/sim/work/div_clk/_primary.dbs
work/sim/work/div_clk/_primary.vhd
work/sim/work/tb_div_clk/verilog.asm
work/sim/work/tb_div_clk/verilog.rw
work/sim/work/tb_div_clk/_primary.dat
work/sim/work/tb_div_clk/_primary.dbs
work/sim/work/tb_div_clk/_primary.vhd
work/sim/work/_info
work/sim/work/_temp/vlog01ywqq
work/sim/work/_temp/vlog02r1rb
work/sim/work/_temp/vlog1s1c8d
work/sim/work/_temp/vlog2q5gtd
work/sim/work/_temp/vlog2qf01e
work/sim/work/_temp/vlog34h7wx
work/sim/work/_temp/vlog5zna2g
work/sim/work/_temp/vlog7hzvm4
work/sim/work/_temp/vlogb16mmk
work/sim/work/_temp/vlogbajaxd
work/sim/work/_temp/vlogi1i97x
work/sim/work/_temp/vlogjic357
work/sim/work/_temp/vlogk8ydvd
work/sim/work/_temp/vlogkhxk6v
work/sim/work/_temp/vlogmvs3z7
work/sim/work/_temp/vlogr362xv
work/sim/work/_temp/vlogrzc3x9
work/sim/work/_temp/vlogsq4ez4
work/sim/work/_temp/vlogwwnhtg
work/sim/work/_temp/vlogyib26n
work/sim/work/_vmake
work/src/div.V.bak
work/src/div_clk.V
work/tb/tb_div.v.bak
work/tb/tb_div_clk.v
work/tb/tb_div_clk.v.bak
work/sim/work/div_clk
work/sim/work/tb_div_clk
work/sim/work/_temp
work/sim/work
work/sim
work/src
work/tb
work
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