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文件名称:proj4

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  • 上传时间:
    2013-12-31
  • 文件大小:
    2.25mb
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    0次
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介绍说明--下载内容来自于网络,使用问题请自行百度

A simple processor for basic assembly commands plus a few more complex commands
(系统自动生成,下载前可以参看下载内容)

下载文件列表

proj4/.lso
proj4/ACE312coursedoc_.coe
proj4/ACE312coursedoc_9.coe
proj4/adder.vhd
proj4/adder4bytes.vhd
proj4/adder4bytes_vhdl.prj
proj4/ALU.vhd
proj4/ALU_control.vhd
proj4/ALU_StageUnit.prj
proj4/ALU_StageUnit.stx
proj4/ALU_StageUnit.vhd
proj4/ALU_StageUnit.xst
proj4/ALU_StageUnit_stx_beh.prj
proj4/ALU_StageUnit_vhdl.prj
proj4/ARM.vhd
proj4/ARM_summary.html
proj4/ARM_vhdl.prj
proj4/control_StageUnit.vhd
proj4/control_StageUnit_vhdl.prj
proj4/countern.vhd
proj4/countern_vhdl.prj
proj4/datapath.vhd
proj4/datapath_vhdl.prj
proj4/decodeUnit.vhd
proj4/decodeUnit_vhdl.prj
proj4/fullAdd.vhd
proj4/fuse.log
proj4/fuse.xmsgs
proj4/fuseRelaunch.cmd
proj4/ifStageUnit.vhd
proj4/ifStageUnit_vhdl.prj
proj4/ipcore_dir/ACE312coursedoc_.coe
proj4/ipcore_dir/ACE312coursedoc_9.coe
proj4/ipcore_dir/blk_mem_gen_ds512.pdf
proj4/ipcore_dir/blk_mem_gen_v6_2_readme.txt
proj4/ipcore_dir/coregen.cgp
proj4/ipcore_dir/coregen.log
proj4/ipcore_dir/create_MEM1024x32.tcl
proj4/ipcore_dir/create_MEM_aRd_sWr_16x32.tcl
proj4/ipcore_dir/create_MEM_RAM_1024x32.tcl
proj4/ipcore_dir/edit_MEM1024x32.tcl
proj4/ipcore_dir/edit_MEM_RAM_1024x32.tcl
proj4/ipcore_dir/MEM1024x32.asy
proj4/ipcore_dir/MEM1024x32.gise
proj4/ipcore_dir/MEM1024x32.mif
proj4/ipcore_dir/MEM1024x32.ngc
proj4/ipcore_dir/MEM1024x32.sym
proj4/ipcore_dir/MEM1024x32.v
proj4/ipcore_dir/MEM1024x32.veo
proj4/ipcore_dir/MEM1024x32.xco
proj4/ipcore_dir/MEM1024x32.xise
proj4/ipcore_dir/MEM1024x32_flist.txt
proj4/ipcore_dir/MEM1024x32_ste/example_design/bmg_wrapper.vhd
proj4/ipcore_dir/MEM1024x32_ste/example_design/MEM1024x32_top.ucf
proj4/ipcore_dir/MEM1024x32_ste/example_design/MEM1024x32_top.vhd
proj4/ipcore_dir/MEM1024x32_ste/example_design/MEM1024x32_top.xdc
proj4/ipcore_dir/MEM1024x32_ste/implement/implement.sh
proj4/ipcore_dir/MEM1024x32_ste/implement/planAhead_rdn.bat
proj4/ipcore_dir/MEM1024x32_ste/implement/planAhead_rdn.sh
proj4/ipcore_dir/MEM1024x32_ste/implement/planAhead_rdn.tcl
proj4/ipcore_dir/MEM1024x32_ste/implement/xst.prj
proj4/ipcore_dir/MEM1024x32_ste/implement/xst.scr
proj4/ipcore_dir/MEM1024x32_xmdf.tcl
proj4/ipcore_dir/MEM_aRd_sWr_16x32.asy
proj4/ipcore_dir/MEM_aRd_sWr_16x32.gise
proj4/ipcore_dir/MEM_aRd_sWr_16x32.ngc
proj4/ipcore_dir/MEM_aRd_sWr_16x32.sym
proj4/ipcore_dir/MEM_aRd_sWr_16x32.v
proj4/ipcore_dir/MEM_aRd_sWr_16x32.veo
proj4/ipcore_dir/MEM_aRd_sWr_16x32.xco
proj4/ipcore_dir/MEM_aRd_sWr_16x32.xise
proj4/ipcore_dir/MEM_aRd_sWr_16x32_flist.txt
proj4/ipcore_dir/MEM_aRd_sWr_16x32_ste/example_design/bmg_wrapper.vhd
proj4/ipcore_dir/MEM_aRd_sWr_16x32_ste/example_design/MEM_aRd_sWr_16x32_top.ucf
proj4/ipcore_dir/MEM_aRd_sWr_16x32_ste/example_design/MEM_aRd_sWr_16x32_top.vhd
proj4/ipcore_dir/MEM_aRd_sWr_16x32_ste/example_design/MEM_aRd_sWr_16x32_top.xdc
proj4/ipcore_dir/MEM_aRd_sWr_16x32_ste/implement/implement.sh
proj4/ipcore_dir/MEM_aRd_sWr_16x32_ste/implement/planAhead_rdn.bat
proj4/ipcore_dir/MEM_aRd_sWr_16x32_ste/implement/planAhead_rdn.sh
proj4/ipcore_dir/MEM_aRd_sWr_16x32_ste/implement/planAhead_rdn.tcl
proj4/ipcore_dir/MEM_aRd_sWr_16x32_ste/implement/xst.prj
proj4/ipcore_dir/MEM_aRd_sWr_16x32_ste/implement/xst.scr
proj4/ipcore_dir/MEM_aRd_sWr_16x32_xmdf.tcl
proj4/ipcore_dir/MEM_RAM_1024x32.asy
proj4/ipcore_dir/MEM_RAM_1024x32.gise
proj4/ipcore_dir/MEM_RAM_1024x32.ngc
proj4/ipcore_dir/MEM_RAM_1024x32.sym
proj4/ipcore_dir/MEM_RAM_1024x32.v
proj4/ipcore_dir/MEM_RAM_1024x32.veo
proj4/ipcore_dir/MEM_RAM_1024x32.xco
proj4/ipcore_dir/MEM_RAM_1024x32.xise
proj4/ipcore_dir/MEM_RAM_1024x32_flist.txt
proj4/ipcore_dir/MEM_RAM_1024x32_ste/example_design/bmg_wrapper.vhd
proj4/ipcore_dir/MEM_RAM_1024x32_ste/example_design/MEM_RAM_1024x32_top.ucf
proj4/ipcore_dir/MEM_RAM_1024x32_ste/example_design/MEM_RAM_1024x32_top.vhd
proj4/ipcore_dir/MEM_RAM_1024x32_ste/example_design/MEM_RAM_1024x32_top.xdc
proj4/ipcore_dir/MEM_RAM_1024x32_ste/implement/implement.sh
proj4/ipcore_dir/MEM_RAM_1024x32_ste/implement/planAhead_rdn.bat
proj4/ipcore_dir/MEM_RAM_1024x32_ste/implement/planAhead_rdn.sh
proj4/ipcore_dir/MEM_RAM_1024x32_ste/implement/planAhead_rdn.tcl
proj4/ipcore_dir/MEM_RAM_1024x32_ste/implement/xst.prj
proj4/ipcore_dir/MEM_RAM_1024x32_ste/implement/xst.scr
proj4/ipcore_dir/MEM_RAM_1024x32_xmdf.tcl
proj4/ipcore_dir/summary.log
proj4/ipcore_dir/tmp/_xmsgs/ngcbuild.xmsgs
proj4/ipcore_dir/tmp/_xmsgs/pn_parser.xmsgs
proj4/ipcore_dir/tmp/_xmsgs/xst.xmsgs
proj4/ipcore_dir/_xmsgs/cg.xmsgs
proj4/ipcore_dir/_xmsgs/pn_parser.xmsgs
proj4/iseconfig/ARM.xreport
proj4/iseconfig/proj4.projectmgr
proj4/isim/isim_usage_statistics.html
proj4/isim/pn_info
proj4/isim/precompiled.exe.sim/ieee/p_2592010699.c
proj4/isim/precompiled.exe.sim/ieee/p_2592010699.didat
proj4/isim/precompiled.exe.sim/ieee/p_2592010699.nt.obj
proj4/isim/precompiled.exe.sim/ieee/p_3499444699.c
proj4/isim/precompiled.exe.sim/ieee/p_3499444699.didat
proj4/isim/precompiled.exe.sim/ieee/p_3499444699.nt.obj
proj4/isim/precompiled.exe.sim/ieee/p_3620187407.c
proj4/isim/precompiled.exe.sim/ieee/p_3620187407.didat
proj4/isim/precompiled.exe.sim/ieee/p_3620187407.nt.obj
proj4/isim/precompiled.exe.sim/vl/p_2533777724.c
proj4/isim/precompiled.exe.sim/

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