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文件名称:VHDL_Source

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [Text]
  • 上传时间：
    2014-01-15
  • 文件大小：
    126.27kb
  • 已下载：
    0次
  • 提 供 者：
    Scot****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

SLC1657 core，一款兼容PIC16c57的MCU内核代码-SLC1657 core which is well compatible with PIC16C57 microcontroller.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

VHDL_Source/
VHDL_Source/Rev2.0/
VHDL_Source/Rev2.0/ALULOGIC/
VHDL_Source/Rev2.0/ALULOGIC/ALULOGIC.VHD
VHDL_Source/Rev2.0/ALULOGIC/TSTBENCH.VHD
VHDL_Source/Rev2.0/BINADDER/
VHDL_Source/Rev2.0/BINADDER/BINADDER.VHD
VHDL_Source/Rev2.0/BINADDER/TSTBENCH.VHD
VHDL_Source/Rev2.0/BUC08NNP/
VHDL_Source/Rev2.0/BUC08NNP/BUC08NNP.VHD
VHDL_Source/Rev2.0/BUC08NNP/TSTBENCH.VHD
VHDL_Source/Rev2.0/BUC11CPP/
VHDL_Source/Rev2.0/BUC11CPP/BUC11CPP.VHD
VHDL_Source/Rev2.0/BUC11CPP/TSTBENCH.VHD
VHDL_Source/Rev2.0/CLOCKDIV/
VHDL_Source/Rev2.0/CLOCKDIV/CLOCKDIV.VHD
VHDL_Source/Rev2.0/CLOCKDIV/TSTBENCH.VHD
VHDL_Source/Rev2.0/INDEXREG/
VHDL_Source/Rev2.0/INDEXREG/INDEXREG.VHD
VHDL_Source/Rev2.0/INDEXREG/TSTBENCH.VHD
VHDL_Source/Rev2.0/INSTRDEC/
VHDL_Source/Rev2.0/INSTRDEC/INSTRDEC.VHD
VHDL_Source/Rev2.0/INSTRDEC/TSTBENCH.VHD
VHDL_Source/Rev2.0/INTRCONV/
VHDL_Source/Rev2.0/INTRCONV/INTRCONV.VHD
VHDL_Source/Rev2.0/INTRCONV/TSTBENCH.VHD
VHDL_Source/Rev2.0/MUX08X04/
VHDL_Source/Rev2.0/MUX08X04/MUX08X04.VHD
VHDL_Source/Rev2.0/MUX08X04/TSTBENCH.VHD
VHDL_Source/Rev2.0/MUX08X08/
VHDL_Source/Rev2.0/MUX08X08/MUX08X08.VHD
VHDL_Source/Rev2.0/MUX08X08/TSTBENCH.VHD
VHDL_Source/Rev2.0/MUX11X04/
VHDL_Source/Rev2.0/MUX11X04/MUX11X04.VHD
VHDL_Source/Rev2.0/MUX11X04/TSTBENCH.VHD
VHDL_Source/Rev2.0/PORTSREG/
VHDL_Source/Rev2.0/PORTSREG/PORTSREG.VHD
VHDL_Source/Rev2.0/PORTSREG/TSTBENCH.VHD
VHDL_Source/Rev2.0/PRESCALE/
VHDL_Source/Rev2.0/PRESCALE/PRESCALE.VHD
VHDL_Source/Rev2.0/PRESCALE/TSTBENCH.VHD
VHDL_Source/Rev2.0/PROGCNTR/
VHDL_Source/Rev2.0/PROGCNTR/PROGCNTR.VHD
VHDL_Source/Rev2.0/PROGCNTR/TSTBENCH.VHD
VHDL_Source/Rev2.0/REG08CNN/
VHDL_Source/Rev2.0/REG08CNN/REG08CNN.VHD
VHDL_Source/Rev2.0/REG08CNN/TSTBENCH.VHD
VHDL_Source/Rev2.0/REG08CPN/
VHDL_Source/Rev2.0/REG08CPN/REG08CPN.VHD
VHDL_Source/Rev2.0/REG08CPN/TSTBENCH.VHD
VHDL_Source/Rev2.0/REG11CNN/
VHDL_Source/Rev2.0/REG11CNN/REG11CNN.VHD
VHDL_Source/Rev2.0/REG11CNN/TSTBENCH.VHD
VHDL_Source/Rev2.0/REG12CRN/
VHDL_Source/Rev2.0/REG12CRN/REG12CRN.VHD
VHDL_Source/Rev2.0/REG12CRN/TSTBENCH.VHD
VHDL_Source/Rev2.0/RESETGEN/
VHDL_Source/Rev2.0/RESETGEN/RESETGEN.VHD
VHDL_Source/Rev2.0/RESETGEN/TSTBENCH.VHD
VHDL_Source/Rev2.0/STATSREG/
VHDL_Source/Rev2.0/STATSREG/STATSREG.VHD
VHDL_Source/Rev2.0/STATSREG/TSTBENCH.VHD
VHDL_Source/Rev2.0/TCOPTREG/
VHDL_Source/Rev2.0/TCOPTREG/TCOPTREG.VHD
VHDL_Source/Rev2.0/TCOPTREG/TSTBENCH.VHD
VHDL_Source/Rev2.0/TIMRCNTR/
VHDL_Source/Rev2.0/TIMRCNTR/TIMRCNTR.VHD
VHDL_Source/Rev2.0/TIMRCNTR/TSTBENCH.VHD
VHDL_Source/Rev2.0/TIMRSYNC/
VHDL_Source/Rev2.0/TIMRSYNC/TIMRSYNC.VHD
VHDL_Source/Rev2.0/TIMRSYNC/TSTBENCH.VHD
VHDL_Source/Rev2.0/TOPLOGIC/
VHDL_Source/Rev2.0/TOPLOGIC/TOPLOGIC.VHD
VHDL_Source/Rev2.0/TOPLOGIC/TSTBENCH.VHD
VHDL_Source/Rev2.0/TOPLOGIC/VECTADDR.TXT
VHDL_Source/Rev2.0/TOPLOGIC/VECTIBNK.TXT
VHDL_Source/Rev2.0/TOPLOGIC/VECTINIT.TXT
VHDL_Source/Rev2.0/TOPLOGIC/VECTINST.TXT
VHDL_Source/Rev2.0/TOPLOGIC/VECTPORT.TXT
VHDL_Source/Rev2.0/TOPLOGIC/VECTPROG.TXT
VHDL_Source/Rev2.0/TOPLOGIC/VECTRBNK.TXT
VHDL_Source/Rev2.0/TOPLOGIC/VECTTIMR.TXT
VHDL_Source/Rev2.0/WATCHDOG/
VHDL_Source/Rev2.0/WATCHDOG/TSTBENCH.VHD
VHDL_Source/Rev2.0/WATCHDOG/WATCHDOG.VHD

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