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文件名称:7.1-5110

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [HTML]
  • 上传时间：
    2014-05-16
  • 文件大小：
    2.86mb
  • 已下载：
    0次
  • 提 供 者：
    qia****
  • 相关连接：
    无
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    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

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FPGA控制诺基亚5110，采用VHDL和Verilog语言，两种语言控制-The FPGA control Nokia 5110, using VHDL and Verilog language, two language control
(系统自动生成,下载前可以参看下载内容)

下载文件列表

7.1 5110/Verilog/db/altsyncram_0hq1.tdf
7.1 5110/Verilog/db/altsyncram_2hq1.tdf
7.1 5110/Verilog/db/altsyncram_9ss3.tdf
7.1 5110/Verilog/db/altsyncram_c7p3.tdf
7.1 5110/Verilog/db/altsyncram_e7p3.tdf
7.1 5110/Verilog/db/altsyncram_ecp3.tdf
7.1 5110/Verilog/db/altsyncram_g7p3.tdf
7.1 5110/Verilog/db/altsyncram_hss3.tdf
7.1 5110/Verilog/db/altsyncram_jss3.tdf
7.1 5110/Verilog/db/altsyncram_ogq1.tdf
7.1 5110/Verilog/db/altsyncram_qgq1.tdf
7.1 5110/Verilog/db/altsyncram_sgq1.tdf
7.1 5110/Verilog/db/cmpr_5cc.tdf
7.1 5110/Verilog/db/cmpr_9cc.tdf
7.1 5110/Verilog/db/cmpr_acc.tdf
7.1 5110/Verilog/db/cntr_0ci.tdf
7.1 5110/Verilog/db/cntr_3ci.tdf
7.1 5110/Verilog/db/cntr_45j.tdf
7.1 5110/Verilog/db/cntr_gui.tdf
7.1 5110/Verilog/db/cntr_m4j.tdf
7.1 5110/Verilog/db/cntr_qbi.tdf
7.1 5110/Verilog/db/cntr_sbi.tdf
7.1 5110/Verilog/db/cntr_u4j.tdf
7.1 5110/Verilog/db/cntr_ubi.tdf
7.1 5110/Verilog/db/cntr_vbi.tdf
7.1 5110/Verilog/db/decode_9oa.tdf
7.1 5110/Verilog/db/decode_rqf.tdf
7.1 5110/Verilog/db/lcd5110.(0).cnf.cdb
7.1 5110/Verilog/db/lcd5110.(0).cnf.hdb
7.1 5110/Verilog/db/lcd5110.asm.qmsg
7.1 5110/Verilog/db/lcd5110.asm_labs.ddb
7.1 5110/Verilog/db/lcd5110.cbx.xml
7.1 5110/Verilog/db/lcd5110.cmp.bpm
7.1 5110/Verilog/db/lcd5110.cmp.cdb
7.1 5110/Verilog/db/lcd5110.cmp.ecobp
7.1 5110/Verilog/db/lcd5110.cmp.hdb
7.1 5110/Verilog/db/lcd5110.cmp.kpt
7.1 5110/Verilog/db/lcd5110.cmp.logdb
7.1 5110/Verilog/db/lcd5110.cmp.rdb
7.1 5110/Verilog/db/lcd5110.cmp.tdb
7.1 5110/Verilog/db/lcd5110.cmp0.ddb
7.1 5110/Verilog/db/lcd5110.cmp2.ddb
7.1 5110/Verilog/db/lcd5110.cmp_merge.kpt
7.1 5110/Verilog/db/lcd5110.db_info
7.1 5110/Verilog/db/lcd5110.eco.cdb
7.1 5110/Verilog/db/lcd5110.fit.qmsg
7.1 5110/Verilog/db/lcd5110.hier_info
7.1 5110/Verilog/db/lcd5110.hif
7.1 5110/Verilog/db/lcd5110.lpc.html
7.1 5110/Verilog/db/lcd5110.lpc.rdb
7.1 5110/Verilog/db/lcd5110.lpc.txt
7.1 5110/Verilog/db/lcd5110.map.bpm
7.1 5110/Verilog/db/lcd5110.map.cdb
7.1 5110/Verilog/db/lcd5110.map.ecobp
7.1 5110/Verilog/db/lcd5110.map.hdb
7.1 5110/Verilog/db/lcd5110.map.kpt
7.1 5110/Verilog/db/lcd5110.map.logdb
7.1 5110/Verilog/db/lcd5110.map.qmsg
7.1 5110/Verilog/db/lcd5110.map_bb.cdb
7.1 5110/Verilog/db/lcd5110.map_bb.hdb
7.1 5110/Verilog/db/lcd5110.map_bb.logdb
7.1 5110/Verilog/db/lcd5110.pre_map.cdb
7.1 5110/Verilog/db/lcd5110.pre_map.hdb
7.1 5110/Verilog/db/lcd5110.ram0_lcd5110_bb3a71fd.hdl.mif
7.1 5110/Verilog/db/lcd5110.rtlv.hdb
7.1 5110/Verilog/db/lcd5110.rtlv_sg.cdb
7.1 5110/Verilog/db/lcd5110.rtlv_sg_swap.cdb
7.1 5110/Verilog/db/lcd5110.sgdiff.cdb
7.1 5110/Verilog/db/lcd5110.sgdiff.hdb
7.1 5110/Verilog/db/lcd5110.sim.cvwf
7.1 5110/Verilog/db/lcd5110.sld_design_entry.sci
7.1 5110/Verilog/db/lcd5110.sld_design_entry_dsc.sci
7.1 5110/Verilog/db/lcd5110.smp_dump.txt
7.1 5110/Verilog/db/lcd5110.syn_hier_info
7.1 5110/Verilog/db/lcd5110.tan.qmsg
7.1 5110/Verilog/db/lcd5110.tis_db_list.ddb
7.1 5110/Verilog/db/lcd5110.tmw_info
7.1 5110/Verilog/db/lcd5110_global_asgn_op.abo
7.1 5110/Verilog/db/mux_7oc.tdf
7.1 5110/Verilog/db/mux_8kb.tdf
7.1 5110/Verilog/db/mux_9oc.tdf
7.1 5110/Verilog/db/mux_boc.tdf
7.1 5110/Verilog/db/prev_cmp_lcd5110.asm.qmsg
7.1 5110/Verilog/db/prev_cmp_lcd5110.fit.qmsg
7.1 5110/Verilog/db/prev_cmp_lcd5110.map.qmsg
7.1 5110/Verilog/db/prev_cmp_lcd5110.qmsg
7.1 5110/Verilog/db/prev_cmp_lcd5110.sim.qmsg
7.1 5110/Verilog/db/prev_cmp_lcd5110.tan.qmsg
7.1 5110/Verilog/db/wed.wsf
7.1 5110/Verilog/incremental_db/compiled_partitions/lcd5110.autos_3e92b2e5d298f5cf757a393f7655ccd81.map.atm
7.1 5110/Verilog/incremental_db/compiled_partitions/lcd5110.autos_3e92b2e5d298f5cf757a393f7655ccd81.map.hdbx
7.1 5110/Verilog/incremental_db/compiled_partitions/lcd5110.autos_3e92b2e5d298f5cf757a393f7655ccd81.map.kpt
7.1 5110/Verilog/incremental_db/compiled_partitions/lcd5110.autos_3e92b2e5d298f5cf757a393f7655ccd81.map.logdb
7.1 5110/Verilog/incremental_db/compiled_partitions/lcd5110.root_partition.cmp.atm
7.1 5110/Verilog/incremental_db/compiled_partitions/lcd5110.root_partition.cmp.dfp
7.1 5110/Verilog/incremental_db/compiled_partitions/lcd5110.root_partition.cmp.hdbx
7.1 5110/Verilog/incremental_db/compiled_partitions/lcd5110.root_partition.cmp.kpt
7.1 5110/Verilog/incremental_db/compiled_partitions/lcd5110.root_partition.cmp.logdb
7.1 5110/Verilog/incremental_db/compiled_partitions/lcd5110.root_partition.cmp.rcf
7.1 5110/Verilog/incremental_db/compiled_partitions/lcd5110.root_partition.map.atm
7.1 5110/Verilog/incremental_db/compiled_partitions/lcd5110.root_partition.map.dpi
7.1 5110/Verilog/incremental_db/compiled_partitions/lcd5110.root_partition.map.hdbx
7.1 5110/Verilog/incremental_db/compiled_partitions/lcd5110.root_partition.map.kpt
7.1 5110/Verilog/incremental_db/compiled_partitions/lcd5110.sldhu_30e344a040fd07e1533c49de5f2d67d1.map.atm
7.1 5110/Verilog/incremental_db/compiled_partitions/lcd5110.sldhu_30e344a040fd07e1533c49de5f2d67d1.map.dpi
7.1 5110/Verilog/incremental_db/compiled_partitions/lcd5110.sldhu_30e344a040fd07e1533c49de5f2d67d1.map.hdbx
7.1 5110/Verilog/incremental_db/compiled_partitions/lcd5110.sldhu_30e344a040fd07e1533c49de5f2d67d1.map.kpt
7.1 5110/Verilog/increme

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