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文件名称:FPGA-mearly-Quartus

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [HTML]
  • 上传时间：
    2014-11-10
  • 文件大小：
    255.39kb
  • 已下载：
    0次
  • 提 供 者：
    叶****
  • 相关连接：
    无
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修正介绍说明

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基于FPGA的状态机程序例程设计。使用的是Mearly型状态机。通过此状态及设计过程来熟悉在Quartus中状态机的设计方法-FPGA based state machine routine design. Using Mearly type state machine. With this status, and the design process to become familiar with the design method in the state machine in Quartus
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下载文件列表

mearly/addrcompiler_47.bsf
mearly/addrcompiler_47.vhd
mearly/addrcompiler_47.vhd.bak
mearly/Block1.bdf
mearly/db/logic_util_heursitic.dat
mearly/db/mux_joc.tdf
mearly/db/prev_cmp_ram_controller.map.qmsg
mearly/db/prev_cmp_ram_controller.qmsg
mearly/db/ram_controller.(0).cnf.cdb
mearly/db/ram_controller.(0).cnf.hdb
mearly/db/ram_controller.(1).cnf.cdb
mearly/db/ram_controller.(1).cnf.hdb
mearly/db/ram_controller.(2).cnf.cdb
mearly/db/ram_controller.(2).cnf.hdb
mearly/db/ram_controller.cbx.xml
mearly/db/ram_controller.cmp.rdb
mearly/db/ram_controller.cmp_merge.kpt
mearly/db/ram_controller.db_info
mearly/db/ram_controller.eco.cdb
mearly/db/ram_controller.eds_overflow
mearly/db/ram_controller.fnsim.cdb
mearly/db/ram_controller.fnsim.hdb
mearly/db/ram_controller.fnsim.qmsg
mearly/db/ram_controller.hier_info
mearly/db/ram_controller.hif
mearly/db/ram_controller.lpc.html
mearly/db/ram_controller.lpc.rdb
mearly/db/ram_controller.lpc.txt
mearly/db/ram_controller.map.bpm
mearly/db/ram_controller.map.cdb
mearly/db/ram_controller.map.ecobp
mearly/db/ram_controller.map.hdb
mearly/db/ram_controller.map.kpt
mearly/db/ram_controller.map.logdb
mearly/db/ram_controller.map.qmsg
mearly/db/ram_controller.map_bb.cdb
mearly/db/ram_controller.map_bb.hdb
mearly/db/ram_controller.map_bb.logdb
mearly/db/ram_controller.pre_map.cdb
mearly/db/ram_controller.pre_map.hdb
mearly/db/ram_controller.rtlv.hdb
mearly/db/ram_controller.rtlv_sg.cdb
mearly/db/ram_controller.rtlv_sg_swap.cdb
mearly/db/ram_controller.sgdiff.cdb
mearly/db/ram_controller.sgdiff.hdb
mearly/db/ram_controller.sim.cvwf
mearly/db/ram_controller.sim.hdb
mearly/db/ram_controller.sim.qmsg
mearly/db/ram_controller.sim.rdb
mearly/db/ram_controller.simfam
mearly/db/ram_controller.sld_design_entry.sci
mearly/db/ram_controller.sld_design_entry_dsc.sci
mearly/db/ram_controller.smart_action.txt
mearly/db/ram_controller.smp_dump.txt
mearly/db/ram_controller.syn_hier_info
mearly/db/ram_controller.tis_db_list.ddb
mearly/db/wed.wsf
mearly/incremental_db/compiled_partitions/ram_controller.root_partition.map.cdb
mearly/incremental_db/compiled_partitions/ram_controller.root_partition.map.dpi
mearly/incremental_db/compiled_partitions/ram_controller.root_partition.map.hdb
mearly/incremental_db/compiled_partitions/ram_controller.root_partition.map.kpt
mearly/incremental_db/README
mearly/ram_controller.bsf
mearly/ram_controller.done
mearly/ram_controller.flow.rpt
mearly/ram_controller.map.rpt
mearly/ram_controller.map.summary
mearly/ram_controller.qpf
mearly/ram_controller.qsf
mearly/ram_controller.qws
mearly/ram_controller.sim.rpt
mearly/ram_controller.vhd
mearly/ram_controller.vhd.bak
mearly/ram_controller.vwf
mearly/incremental_db/compiled_partitions
mearly/db
mearly/incremental_db
mearly

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