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文件名称:FIFO_BUFFER

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [HTML]
  • 上传时间：
    2015-07-13
  • 文件大小：
    3.72mb
  • 已下载：
    0次
  • 提 供 者：
    lit***
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

先入先出的缓冲器，可以实现8位的读、写数据操作。-buffer of first-in first-out circuit can ，Realization 8-bit. The number of read and wirte operation is stopped.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

FIFO_BUFFER/FIFO_BUFFER.qpf
FIFO_BUFFER/FIFO_BUFFER.qsf
FIFO_BUFFER/db/FIFO_BUFFER.db_info
FIFO_BUFFER/db/FIFO_BUFFER.cbx.xml
FIFO_BUFFER/db/FIFO_BUFFER.hif
FIFO_BUFFER/db/FIFO_BUFFER.hier_info
FIFO_BUFFER/db/altsyncram_j7e1.tdf
FIFO_BUFFER/db/FIFO_BUFFER.(1).cnf.cdb
FIFO_BUFFER/db/FIFO_BUFFER.(1).cnf.hdb
FIFO_BUFFER/db/FIFO_BUFFER.(2).cnf.cdb
FIFO_BUFFER/db/FIFO_BUFFER.(2).cnf.hdb
FIFO_BUFFER/db/FIFO_BUFFER.syn_hier_info
FIFO_BUFFER/db/FIFO_BUFFER.map.ecobp
FIFO_BUFFER/db/FIFO_BUFFER.map.kpt
FIFO_BUFFER/db/FIFO_BUFFER.cmp_merge.kpt
FIFO_BUFFER/db/FIFO_BUFFER.cmp.kpt
FIFO_BUFFER/db/FIFO_BUFFER.rpp.qmsg
FIFO_BUFFER/db/FIFO_BUFFER.sgate.rvd
FIFO_BUFFER/db/FIFO_BUFFER.sgate_sm.rvd
FIFO_BUFFER/db/prev_cmp_FIFO_BUFFER.qmsg
FIFO_BUFFER/db/prev_cmp_FIFO_BUFFER.map.qmsg
FIFO_BUFFER/db/prev_cmp_FIFO_BUFFER.fit.qmsg
FIFO_BUFFER/db/prev_cmp_FIFO_BUFFER.asm.qmsg
FIFO_BUFFER/db/prev_cmp_FIFO_BUFFER.tan.qmsg
FIFO_BUFFER/db/prev_cmp_FIFO_BUFFER.eda.qmsg
FIFO_BUFFER/db/FIFO_BUFFER.map.qmsg
FIFO_BUFFER/db/FIFO_BUFFER.(0).cnf.cdb
FIFO_BUFFER/db/FIFO_BUFFER.(0).cnf.hdb
FIFO_BUFFER/db/FIFO_BUFFER.rtlv_sg.cdb
FIFO_BUFFER/db/FIFO_BUFFER.rtlv.hdb
FIFO_BUFFER/db/FIFO_BUFFER.rtlv_sg_swap.cdb
FIFO_BUFFER/db/FIFO_BUFFER.lpc.txt
FIFO_BUFFER/db/FIFO_BUFFER.lpc.html
FIFO_BUFFER/db/FIFO_BUFFER.lpc.rdb
FIFO_BUFFER/db/FIFO_BUFFER.pre_map.hdb
FIFO_BUFFER/db/FIFO_BUFFER.pre_map.cdb
FIFO_BUFFER/db/FIFO_BUFFER.map_bb.logdb
FIFO_BUFFER/db/FIFO_BUFFER.sgdiff.cdb
FIFO_BUFFER/db/FIFO_BUFFER.sgdiff.hdb
FIFO_BUFFER/db/FIFO_BUFFER.sld_design_entry_dsc.sci
FIFO_BUFFER/db/FIFO_BUFFER.map_bb.cdb
FIFO_BUFFER/db/FIFO_BUFFER.map_bb.hdb
FIFO_BUFFER/db/FIFO_BUFFER.map.cdb
FIFO_BUFFER/db/FIFO_BUFFER.map.hdb
FIFO_BUFFER/db/FIFO_BUFFER.map.logdb
FIFO_BUFFER/db/FIFO_BUFFER.map.bpm
FIFO_BUFFER/db/FIFO_BUFFER.fit.qmsg
FIFO_BUFFER/db/FIFO_BUFFER.cmp.logdb
FIFO_BUFFER/db/FIFO_BUFFER.cmp.bpm
FIFO_BUFFER/db/FIFO_BUFFER.cmp.ecobp
FIFO_BUFFER/db/FIFO_BUFFER.asm.qmsg
FIFO_BUFFER/db/FIFO_BUFFER.asm_labs.ddb
FIFO_BUFFER/db/FIFO_BUFFER.tan.qmsg
FIFO_BUFFER/db/FIFO_BUFFER.cmp.tdb
FIFO_BUFFER/db/FIFO_BUFFER.cmp0.ddb
FIFO_BUFFER/db/FIFO_BUFFER.cmp.cdb
FIFO_BUFFER/db/FIFO_BUFFER.eda.qmsg
FIFO_BUFFER/db/FIFO_BUFFER.cmp.hdb
FIFO_BUFFER/db/FIFO_BUFFER.cmp.rdb
FIFO_BUFFER/db/FIFO_BUFFER.tis_db_list.ddb
FIFO_BUFFER/db/FIFO_BUFFER.sld_design_entry.sci
FIFO_BUFFER/db/FIFO_BUFFER.eco.cdb
FIFO_BUFFER/db/FIFO_BUFFER.tmw_info
FIFO_BUFFER/FIFO_BUFFER.map.summary
FIFO_BUFFER/incremental_db/compiled_partitions/FIFO_BUFFER.root_partition.map.kpt
FIFO_BUFFER/incremental_db/compiled_partitions/FIFO_BUFFER.root_partition.map.atm
FIFO_BUFFER/incremental_db/compiled_partitions/FIFO_BUFFER.root_partition.map.hdbx
FIFO_BUFFER/incremental_db/compiled_partitions/FIFO_BUFFER.root_partition.cmp.rcf
FIFO_BUFFER/incremental_db/compiled_partitions/FIFO_BUFFER.root_partition.cmp.hdbx
FIFO_BUFFER/incremental_db/compiled_partitions/FIFO_BUFFER.root_partition.cmp.atm
FIFO_BUFFER/incremental_db/compiled_partitions/FIFO_BUFFER.root_partition.cmp.logdb
FIFO_BUFFER/incremental_db/compiled_partitions/FIFO_BUFFER.root_partition.cmp.kpt
FIFO_BUFFER/incremental_db/compiled_partitions/FIFO_BUFFER.root_partition.map.dpi
FIFO_BUFFER/incremental_db/compiled_partitions/FIFO_BUFFER.root_partition.cmp.dfp
FIFO_BUFFER/incremental_db/README
FIFO_BUFFER/FIFO_BUFFER.pin
FIFO_BUFFER/FIFO_BUFFER.fit.summary
FIFO_BUFFER/FIFO_BUFFER.sof
FIFO_BUFFER/FIFO_BUFFER.pof
FIFO_BUFFER/FIFO_BUFFER.tan.summary
FIFO_BUFFER/simulation/modelsim/FIFO_BUFFER_modelsim.xrf
FIFO_BUFFER/simulation/modelsim/FIFO_BUFFER.vo
FIFO_BUFFER/simulation/modelsim/FIFO_BUFFER_v.sdo
FIFO_BUFFER/simulation/modelsim/FIFO_BUFFER_run_msim_rtl_verilog.do
FIFO_BUFFER/simulation/modelsim/verilog_libs/altera_ver/_info
FIFO_BUFFER/simulation/modelsim/verilog_libs/altera_ver/_lib.qdb
FIFO_BUFFER/simulation/modelsim/verilog_libs/altera_ver/_lib1_0.qpg
FIFO_BUFFER/simulation/modelsim/verilog_libs/altera_ver/_lib1_0.qdb
FIFO_BUFFER/simulation/modelsim/verilog_libs/altera_ver/_vmake
FIFO_BUFFER/simulation/modelsim/verilog_libs/altera_ver/_lib1_1.qpg
FIFO_BUFFER/simulation/modelsim/verilog_libs/altera_ver/_lib1_1.qdb
FIFO_BUFFER/simulation/modelsim/verilog_libs/lpm_ver/_info
FIFO_BUFFER/simulation/modelsim/verilog_libs/lpm_ver/_lib.qdb
FIFO_BUFFER/simulation/modelsim/verilog_libs/lpm_ver/_lib1_0.qpg
FIFO_BUFFER/simulation/modelsim/verilog_libs/lpm_ver/_lib1_0.qdb
FIFO_BUFFER/simulation/modelsim/verilog_libs/lpm_ver/_vmake
FIFO_BUFFER/simulation/modelsim/verilog_libs/lpm_ver/_lib1_1.qpg
FIFO_BUFFER/simulation/modelsim/verilog_libs/lpm_ver/_lib1_1.qdb
FIFO_BUFFER/simulation/modelsim/verilog_libs/sgate_ver/_info
FIFO_BUFFER/simulation/modelsim/verilog_libs/sgate_ver/_lib.qdb
FIFO_BUFFER/simulation/modelsim/verilog_libs/sgate_ver/_lib1_0.qpg
FIFO_BUFFER/simulation/modelsim/verilog_libs/sgate_ver/_lib1_0.qdb
FIFO_BUFFER/simulation/modelsim/verilog_libs/sgate_ver/_vmake
FIFO_BUFFER/simulation/modelsim/verilog_libs/altera_mf_ver/_info
FIFO_BUFFER/simulation/modelsim/verilog_libs/altera_mf_ver/_lib.qdb
FIFO_BUFFER/simulation/modelsim/verilog_libs/altera_mf_ver/_vmake
FIFO_BUFFER/simulation/modelsim/verilo

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