文件名称:spimaster.tar
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SPI Interface Master Control RTL Verilog Code
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下载文件列表
spimaster/
spimaster/branches/
spimaster/tags/
spimaster/web_uploads/
spimaster/trunk/
spimaster/trunk/RTL/
spimaster/trunk/RTL/sm_fifoRTL.v
spimaster/trunk/RTL/readWriteSDBlock.v
spimaster/trunk/RTL/timescale.v
spimaster/trunk/RTL/spiMasterWishBoneBI.v
spimaster/trunk/RTL/sm_TxFifoBI.v
spimaster/trunk/RTL/spiCtrl.v
spimaster/trunk/RTL/spiMaster.v
spimaster/trunk/RTL/sm_TxFifo.v
spimaster/trunk/RTL/sm_dpMem_dc.v
spimaster/trunk/RTL/spiTxRxData.v
spimaster/trunk/RTL/spiMaster_defines.v
spimaster/trunk/RTL/sm_RxFifo.v
spimaster/trunk/RTL/ctrlStsRegBI.v
spimaster/trunk/RTL/initSD.v
spimaster/trunk/RTL/sendCmd.v
spimaster/trunk/RTL/readWriteSPIWireData.v
spimaster/trunk/RTL/sm_RxFifoBI.v
spimaster/trunk/bench/
spimaster/trunk/bench/testHarness.v
spimaster/trunk/bench/testCase0.v
spimaster/trunk/model/
spimaster/trunk/model/sdModel.v
spimaster/trunk/model/wb_master_model.v
spimaster/trunk/Aldec/
spimaster/trunk/Aldec/design0/
spimaster/trunk/Aldec/design0/fsm.set
spimaster/trunk/Aldec/design0/src/
spimaster/trunk/Aldec/design0/src/initSD.asf
spimaster/trunk/Aldec/design0/src/spiCtrl.asf
spimaster/trunk/Aldec/design0/src/sendCmd.asf
spimaster/trunk/Aldec/design0/src/readWriteSPIWireData.asf
spimaster/trunk/Aldec/design0/src/readWriteSDBlock.asf
spimaster/trunk/Aldec/design0/design0.adf
spimaster/trunk/sim/
spimaster/trunk/sim/run.do
spimaster/trunk/sim/wave.do
spimaster/trunk/sim/filelist.icarus
spimaster/trunk/sim/compile.do
spimaster/trunk/sim/run_icarus.bat
spimaster/trunk/sim/build_icarus.bat
spimaster/trunk/sim/modelsim.ini
spimaster/trunk/syn/
spimaster/trunk/syn/spiMaster.qsf
spimaster/trunk/syn/spiMaster.qpf
spimaster/trunk/doc/
spimaster/trunk/doc/src/
spimaster/trunk/doc/src/spiMaster_Specification.sxw
spimaster/trunk/doc/spiMaster_Specification.pdf
spimaster/trunk/doc/spiMaster_FSM.pdf
spimaster/branches/
spimaster/tags/
spimaster/web_uploads/
spimaster/trunk/
spimaster/trunk/RTL/
spimaster/trunk/RTL/sm_fifoRTL.v
spimaster/trunk/RTL/readWriteSDBlock.v
spimaster/trunk/RTL/timescale.v
spimaster/trunk/RTL/spiMasterWishBoneBI.v
spimaster/trunk/RTL/sm_TxFifoBI.v
spimaster/trunk/RTL/spiCtrl.v
spimaster/trunk/RTL/spiMaster.v
spimaster/trunk/RTL/sm_TxFifo.v
spimaster/trunk/RTL/sm_dpMem_dc.v
spimaster/trunk/RTL/spiTxRxData.v
spimaster/trunk/RTL/spiMaster_defines.v
spimaster/trunk/RTL/sm_RxFifo.v
spimaster/trunk/RTL/ctrlStsRegBI.v
spimaster/trunk/RTL/initSD.v
spimaster/trunk/RTL/sendCmd.v
spimaster/trunk/RTL/readWriteSPIWireData.v
spimaster/trunk/RTL/sm_RxFifoBI.v
spimaster/trunk/bench/
spimaster/trunk/bench/testHarness.v
spimaster/trunk/bench/testCase0.v
spimaster/trunk/model/
spimaster/trunk/model/sdModel.v
spimaster/trunk/model/wb_master_model.v
spimaster/trunk/Aldec/
spimaster/trunk/Aldec/design0/
spimaster/trunk/Aldec/design0/fsm.set
spimaster/trunk/Aldec/design0/src/
spimaster/trunk/Aldec/design0/src/initSD.asf
spimaster/trunk/Aldec/design0/src/spiCtrl.asf
spimaster/trunk/Aldec/design0/src/sendCmd.asf
spimaster/trunk/Aldec/design0/src/readWriteSPIWireData.asf
spimaster/trunk/Aldec/design0/src/readWriteSDBlock.asf
spimaster/trunk/Aldec/design0/design0.adf
spimaster/trunk/sim/
spimaster/trunk/sim/run.do
spimaster/trunk/sim/wave.do
spimaster/trunk/sim/filelist.icarus
spimaster/trunk/sim/compile.do
spimaster/trunk/sim/run_icarus.bat
spimaster/trunk/sim/build_icarus.bat
spimaster/trunk/sim/modelsim.ini
spimaster/trunk/syn/
spimaster/trunk/syn/spiMaster.qsf
spimaster/trunk/syn/spiMaster.qpf
spimaster/trunk/doc/
spimaster/trunk/doc/src/
spimaster/trunk/doc/src/spiMaster_Specification.sxw
spimaster/trunk/doc/spiMaster_Specification.pdf
spimaster/trunk/doc/spiMaster_FSM.pdf