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文件名称:Verilog-master

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2016-05-02
  • 文件大小：
    28.26mb
  • 已下载：
    1次
  • 提 供 者：
    Tao ****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

包含多个verilog源码，主要是AD7606的官方驱动，备注详细，学习参考。-Comprising a plurality of verilog source code, mainly AD7606 official driver, detailed notes, study reference.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

Verilog-master/
Verilog-master/.gitignore
Verilog-master/AD7606URAT/
Verilog-master/AD7606URAT/AAD7606.v
Verilog-master/AD7606URAT/AAD7606.v.bak
Verilog-master/AD7606URAT/RAM.qip
Verilog-master/AD7606URAT/RAM.v
Verilog-master/AD7606URAT/RAM_bb.v
Verilog-master/AD7606URAT/RAM_inst.v
Verilog-master/AD7606URAT/URAT_TX.v
Verilog-master/AD7606URAT/URAT_TX.v.bak
Verilog-master/AD7606URAT/ad7606.v
Verilog-master/AD7606URAT/ad7606.v.bak
Verilog-master/AD7606URAT/ad7606_M.v
Verilog-master/AD7606URAT/ad7606_M.v.bak
Verilog-master/AD7606URAT/ad_urat.asm.rpt
Verilog-master/AD7606URAT/ad_urat.cdf
Verilog-master/AD7606URAT/ad_urat.done
Verilog-master/AD7606URAT/ad_urat.eda.rpt
Verilog-master/AD7606URAT/ad_urat.fit.rpt
Verilog-master/AD7606URAT/ad_urat.fit.smsg
Verilog-master/AD7606URAT/ad_urat.fit.summary
Verilog-master/AD7606URAT/ad_urat.flow.rpt
Verilog-master/AD7606URAT/ad_urat.jdi
Verilog-master/AD7606URAT/ad_urat.map.rpt
Verilog-master/AD7606URAT/ad_urat.map.smsg
Verilog-master/AD7606URAT/ad_urat.map.summary
Verilog-master/AD7606URAT/ad_urat.merge.rpt
Verilog-master/AD7606URAT/ad_urat.merge.summary
Verilog-master/AD7606URAT/ad_urat.pin
Verilog-master/AD7606URAT/ad_urat.pof
Verilog-master/AD7606URAT/ad_urat.qpf
Verilog-master/AD7606URAT/ad_urat.qsf
Verilog-master/AD7606URAT/ad_urat.qws
Verilog-master/AD7606URAT/ad_urat.sof
Verilog-master/AD7606URAT/ad_urat.sta.rpt
Verilog-master/AD7606URAT/ad_urat.sta.summary
Verilog-master/AD7606URAT/ad_urat.tcl
Verilog-master/AD7606URAT/ad_urat.tis_db_list.ddb
Verilog-master/AD7606URAT/ad_urat.v
Verilog-master/AD7606URAT/ad_urat.v.bak
Verilog-master/AD7606URAT/ad_urat_assignment_defaults.qdf
Verilog-master/AD7606URAT/ad_urat_nativelink_simulation.rpt
Verilog-master/AD7606URAT/db/
Verilog-master/AD7606URAT/db/.cmp.kpt
Verilog-master/AD7606URAT/db/ad_urat.(0).cnf.cdb
Verilog-master/AD7606URAT/db/ad_urat.(0).cnf.hdb
Verilog-master/AD7606URAT/db/ad_urat.(1).cnf.cdb
Verilog-master/AD7606URAT/db/ad_urat.(1).cnf.hdb
Verilog-master/AD7606URAT/db/ad_urat.(2).cnf.cdb
Verilog-master/AD7606URAT/db/ad_urat.(2).cnf.hdb
Verilog-master/AD7606URAT/db/ad_urat.(3).cnf.cdb
Verilog-master/AD7606URAT/db/ad_urat.(3).cnf.hdb
Verilog-master/AD7606URAT/db/ad_urat.(4).cnf.cdb
Verilog-master/AD7606URAT/db/ad_urat.(4).cnf.hdb
Verilog-master/AD7606URAT/db/ad_urat.(5).cnf.cdb
Verilog-master/AD7606URAT/db/ad_urat.(5).cnf.hdb
Verilog-master/AD7606URAT/db/ad_urat.ace_cmp.bpm
Verilog-master/AD7606URAT/db/ad_urat.ace_cmp.cdb
Verilog-master/AD7606URAT/db/ad_urat.ace_cmp.hdb
Verilog-master/AD7606URAT/db/ad_urat.acvq.rdb
Verilog-master/AD7606URAT/db/ad_urat.asm.qmsg
Verilog-master/AD7606URAT/db/ad_urat.asm.rdb
Verilog-master/AD7606URAT/db/ad_urat.asm_labs.ddb
Verilog-master/AD7606URAT/db/ad_urat.atom_fit.nvd
Verilog-master/AD7606URAT/db/ad_urat.cbx.xml
Verilog-master/AD7606URAT/db/ad_urat.cmp.bpm
Verilog-master/AD7606URAT/db/ad_urat.cmp.cdb
Verilog-master/AD7606URAT/db/ad_urat.cmp.hdb
Verilog-master/AD7606URAT/db/ad_urat.cmp.idb
Verilog-master/AD7606URAT/db/ad_urat.cmp.logdb
Verilog-master/AD7606URAT/db/ad_urat.cmp.rdb
Verilog-master/AD7606URAT/db/ad_urat.cmp_merge.kpt
Verilog-master/AD7606URAT/db/ad_urat.cycloneive_io_sim_cache.31um_ff_1200mv_0c_fast.hsd
Verilog-master/AD7606URAT/db/ad_urat.cycloneive_io_sim_cache.31um_ss_1200mv_0c_slow.hsd
Verilog-master/AD7606URAT/db/ad_urat.cycloneive_io_sim_cache.31um_ss_1200mv_85c_slow.hsd
Verilog-master/AD7606URAT/db/ad_urat.db_info
Verilog-master/AD7606URAT/db/ad_urat.eco.cdb
Verilog-master/AD7606URAT/db/ad_urat.eda.qmsg
Verilog-master/AD7606URAT/db/ad_urat.fit.qmsg
Verilog-master/AD7606URAT/db/ad_urat.hier_info
Verilog-master/AD7606URAT/db/ad_urat.hif
Verilog-master/AD7606URAT/db/ad_urat.ipinfo
Verilog-master/AD7606URAT/db/ad_urat.lpc.html
Verilog-master/AD7606URAT/db/ad_urat.lpc.rdb
Verilog-master/AD7606URAT/db/ad_urat.lpc.txt
Verilog-master/AD7606URAT/db/ad_urat.map.ammdb
Verilog-master/AD7606URAT/db/ad_urat.map.bpm
Verilog-master/AD7606URAT/db/ad_urat.map.cdb
Verilog-master/AD7606URAT/db/ad_urat.map.hdb
Verilog-master/AD7606URAT/db/ad_urat.map.kpt
Verilog-master/AD7606URAT/db/ad_urat.map.logdb
Verilog-master/AD7606URAT/db/ad_urat.map.qmsg
Verilog-master/AD7606URAT/db/ad_urat.map.rcfdb
Verilog-master/AD7606URAT/db/ad_urat.map.rdb
Verilog-master/AD7606URAT/db/ad_urat.map_bb.cdb
Verilog-master/AD7606URAT/db/ad_urat.map_bb.hdb
Verilog-master/AD7606URAT/db/ad_urat.map_bb.logdb
Verilog-master/AD7606URAT/db/ad_urat.merge.qmsg
Verilog-master/AD7606URAT/db/ad_urat.npp.qmsg
Verilog-master/AD7606URAT/db/ad_urat.pplq.rdb
Verilog-master/AD7606URAT/db/ad_urat.pre_map.hdb
Verilog-master/AD7606URAT/db/ad_urat.pti_db_list.ddb
Verilog-master/AD7606URAT/db/ad_urat.quartus_db.empty-vpr.rcfdb
Verilog-master/AD7606URAT/db/ad_urat.quartus_db.retry.rcfdb
Verilog-master/AD7606URAT/db/ad_urat.root_partition.map.reg_db.cdb
Verilog-master/AD7606URAT/db/ad_urat.routing.rdb
Verilog-master/AD7606URAT/db/ad_urat.rtlv.hdb
Verilog-master/AD7606URAT/db/ad_urat.rtlv_sg.cdb
Verilog-master/AD7606URAT/db/ad_urat.rtlv_sg_swap.cdb
Verilog-master/AD7606URAT/db/ad_urat.sgate.nvd
Verilog-master/AD7606URAT/db/ad_urat.sgate_sm.nvd
Verilo

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