文件名称:145103015
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- 上传时间:2016-11-26
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文件大小:1019.18kb
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Verilog source code for using keypad module with zybo fpga board to take input and show output to onboard leds and led module connected to GPIO
(系统自动生成,下载前可以参看下载内容)
下载文件列表
145103015/145103015.cache/wt/java_command_handlers.wdf
145103015/145103015.cache/wt/project.wpc
145103015/145103015.cache/wt/synthesis.wdf
145103015/145103015.cache/wt/synthesis_details.wdf
145103015/145103015.cache/wt/webtalk_pa.xml
145103015/145103015.hw/145103015.lpr
145103015/145103015.hw/hw_1/hw.xml
145103015/145103015.ip_user_files/ip/clk_core/clk_core.veo
145103015/145103015.ip_user_files/ip/clk_core/clk_core_stub.v
145103015/145103015.ip_user_files/ip/clk_core/clk_core_stub.vhdl
145103015/145103015.ip_user_files/ipstatic/clk_wiz_v5_3_1/mmcm_pll_drp_func_7s_mmcm.vh
145103015/145103015.ip_user_files/ipstatic/clk_wiz_v5_3_1/mmcm_pll_drp_func_7s_pll.vh
145103015/145103015.ip_user_files/ipstatic/clk_wiz_v5_3_1/mmcm_pll_drp_func_us_mmcm.vh
145103015/145103015.ip_user_files/ipstatic/clk_wiz_v5_3_1/mmcm_pll_drp_func_us_pll.vh
145103015/145103015.ip_user_files/README.txt
145103015/145103015.ip_user_files/sim_scripts/clk_core/activehdl/clk_core.sh
145103015/145103015.ip_user_files/sim_scripts/clk_core/activehdl/clk_core.udo
145103015/145103015.ip_user_files/sim_scripts/clk_core/activehdl/compile.do
145103015/145103015.ip_user_files/sim_scripts/clk_core/activehdl/file_info.txt
145103015/145103015.ip_user_files/sim_scripts/clk_core/activehdl/glbl.v
145103015/145103015.ip_user_files/sim_scripts/clk_core/activehdl/README.txt
145103015/145103015.ip_user_files/sim_scripts/clk_core/activehdl/simulate.do
145103015/145103015.ip_user_files/sim_scripts/clk_core/activehdl/wave.do
145103015/145103015.ip_user_files/sim_scripts/clk_core/ies/clk_core.sh
145103015/145103015.ip_user_files/sim_scripts/clk_core/ies/file_info.txt
145103015/145103015.ip_user_files/sim_scripts/clk_core/ies/glbl.v
145103015/145103015.ip_user_files/sim_scripts/clk_core/ies/README.txt
145103015/145103015.ip_user_files/sim_scripts/clk_core/ies/run.f
145103015/145103015.ip_user_files/sim_scripts/clk_core/modelsim/clk_core.sh
145103015/145103015.ip_user_files/sim_scripts/clk_core/modelsim/clk_core.udo
145103015/145103015.ip_user_files/sim_scripts/clk_core/modelsim/compile.do
145103015/145103015.ip_user_files/sim_scripts/clk_core/modelsim/file_info.txt
145103015/145103015.ip_user_files/sim_scripts/clk_core/modelsim/glbl.v
145103015/145103015.ip_user_files/sim_scripts/clk_core/modelsim/README.txt
145103015/145103015.ip_user_files/sim_scripts/clk_core/modelsim/simulate.do
145103015/145103015.ip_user_files/sim_scripts/clk_core/modelsim/wave.do
145103015/145103015.ip_user_files/sim_scripts/clk_core/questa/clk_core.sh
145103015/145103015.ip_user_files/sim_scripts/clk_core/questa/clk_core.udo
145103015/145103015.ip_user_files/sim_scripts/clk_core/questa/compile.do
145103015/145103015.ip_user_files/sim_scripts/clk_core/questa/elaborate.do
145103015/145103015.ip_user_files/sim_scripts/clk_core/questa/file_info.txt
145103015/145103015.ip_user_files/sim_scripts/clk_core/questa/glbl.v
145103015/145103015.ip_user_files/sim_scripts/clk_core/questa/README.txt
145103015/145103015.ip_user_files/sim_scripts/clk_core/questa/simulate.do
145103015/145103015.ip_user_files/sim_scripts/clk_core/questa/wave.do
145103015/145103015.ip_user_files/sim_scripts/clk_core/README.txt
145103015/145103015.ip_user_files/sim_scripts/clk_core/riviera/clk_core.sh
145103015/145103015.ip_user_files/sim_scripts/clk_core/riviera/clk_core.udo
145103015/145103015.ip_user_files/sim_scripts/clk_core/riviera/compile.do
145103015/145103015.ip_user_files/sim_scripts/clk_core/riviera/file_info.txt
145103015/145103015.ip_user_files/sim_scripts/clk_core/riviera/glbl.v
145103015/145103015.ip_user_files/sim_scripts/clk_core/riviera/README.txt
145103015/145103015.ip_user_files/sim_scripts/clk_core/riviera/simulate.do
145103015/145103015.ip_user_files/sim_scripts/clk_core/riviera/wave.do
145103015/145103015.ip_user_files/sim_scripts/clk_core/vcs/clk_core.sh
145103015/145103015.ip_user_files/sim_scripts/clk_core/vcs/file_info.txt
145103015/145103015.ip_user_files/sim_scripts/clk_core/vcs/glbl.v
145103015/145103015.ip_user_files/sim_scripts/clk_core/vcs/README.txt
145103015/145103015.ip_user_files/sim_scripts/clk_core/vcs/simulate.do
145103015/145103015.ip_user_files/sim_scripts/clk_core/xsim/clk_core.sh
145103015/145103015.ip_user_files/sim_scripts/clk_core/xsim/cmd.tcl
145103015/145103015.ip_user_files/sim_scripts/clk_core/xsim/elab.opt
145103015/145103015.ip_user_files/sim_scripts/clk_core/xsim/file_info.txt
145103015/145103015.ip_user_files/sim_scripts/clk_core/xsim/glbl.v
145103015/145103015.ip_user_files/sim_scripts/clk_core/xsim/README.txt
145103015/145103015.ip_user_files/sim_scripts/clk_core/xsim/vhdl.prj
145103015/145103015.ip_user_files/sim_scripts/clk_core/xsim/vlog.prj
145103015/145103015.ip_user_files/sim_scripts/clk_core/xsim/xsim.ini
145103015/145103015.runs/.jobs/vrs_config_1.xml
145103015/145103015.runs/.jobs/vrs_config_10.xml
145103015/145103015.runs/.jobs/vrs_config_11.xml
145103015/145103015.runs/.jobs/vrs_config_12.xml
145103015/145103015.runs/.jobs/vrs_config_13.xml
145103015/145103015.runs/.jobs/vrs_config_2.xml
145103015/145103015.runs/.jobs/vrs_config_3.xml
145103015/145103015.runs/.jobs/vrs_config_4.xml
145103015/145103015.cache/wt/project.wpc
145103015/145103015.cache/wt/synthesis.wdf
145103015/145103015.cache/wt/synthesis_details.wdf
145103015/145103015.cache/wt/webtalk_pa.xml
145103015/145103015.hw/145103015.lpr
145103015/145103015.hw/hw_1/hw.xml
145103015/145103015.ip_user_files/ip/clk_core/clk_core.veo
145103015/145103015.ip_user_files/ip/clk_core/clk_core_stub.v
145103015/145103015.ip_user_files/ip/clk_core/clk_core_stub.vhdl
145103015/145103015.ip_user_files/ipstatic/clk_wiz_v5_3_1/mmcm_pll_drp_func_7s_mmcm.vh
145103015/145103015.ip_user_files/ipstatic/clk_wiz_v5_3_1/mmcm_pll_drp_func_7s_pll.vh
145103015/145103015.ip_user_files/ipstatic/clk_wiz_v5_3_1/mmcm_pll_drp_func_us_mmcm.vh
145103015/145103015.ip_user_files/ipstatic/clk_wiz_v5_3_1/mmcm_pll_drp_func_us_pll.vh
145103015/145103015.ip_user_files/README.txt
145103015/145103015.ip_user_files/sim_scripts/clk_core/activehdl/clk_core.sh
145103015/145103015.ip_user_files/sim_scripts/clk_core/activehdl/clk_core.udo
145103015/145103015.ip_user_files/sim_scripts/clk_core/activehdl/compile.do
145103015/145103015.ip_user_files/sim_scripts/clk_core/activehdl/file_info.txt
145103015/145103015.ip_user_files/sim_scripts/clk_core/activehdl/glbl.v
145103015/145103015.ip_user_files/sim_scripts/clk_core/activehdl/README.txt
145103015/145103015.ip_user_files/sim_scripts/clk_core/activehdl/simulate.do
145103015/145103015.ip_user_files/sim_scripts/clk_core/activehdl/wave.do
145103015/145103015.ip_user_files/sim_scripts/clk_core/ies/clk_core.sh
145103015/145103015.ip_user_files/sim_scripts/clk_core/ies/file_info.txt
145103015/145103015.ip_user_files/sim_scripts/clk_core/ies/glbl.v
145103015/145103015.ip_user_files/sim_scripts/clk_core/ies/README.txt
145103015/145103015.ip_user_files/sim_scripts/clk_core/ies/run.f
145103015/145103015.ip_user_files/sim_scripts/clk_core/modelsim/clk_core.sh
145103015/145103015.ip_user_files/sim_scripts/clk_core/modelsim/clk_core.udo
145103015/145103015.ip_user_files/sim_scripts/clk_core/modelsim/compile.do
145103015/145103015.ip_user_files/sim_scripts/clk_core/modelsim/file_info.txt
145103015/145103015.ip_user_files/sim_scripts/clk_core/modelsim/glbl.v
145103015/145103015.ip_user_files/sim_scripts/clk_core/modelsim/README.txt
145103015/145103015.ip_user_files/sim_scripts/clk_core/modelsim/simulate.do
145103015/145103015.ip_user_files/sim_scripts/clk_core/modelsim/wave.do
145103015/145103015.ip_user_files/sim_scripts/clk_core/questa/clk_core.sh
145103015/145103015.ip_user_files/sim_scripts/clk_core/questa/clk_core.udo
145103015/145103015.ip_user_files/sim_scripts/clk_core/questa/compile.do
145103015/145103015.ip_user_files/sim_scripts/clk_core/questa/elaborate.do
145103015/145103015.ip_user_files/sim_scripts/clk_core/questa/file_info.txt
145103015/145103015.ip_user_files/sim_scripts/clk_core/questa/glbl.v
145103015/145103015.ip_user_files/sim_scripts/clk_core/questa/README.txt
145103015/145103015.ip_user_files/sim_scripts/clk_core/questa/simulate.do
145103015/145103015.ip_user_files/sim_scripts/clk_core/questa/wave.do
145103015/145103015.ip_user_files/sim_scripts/clk_core/README.txt
145103015/145103015.ip_user_files/sim_scripts/clk_core/riviera/clk_core.sh
145103015/145103015.ip_user_files/sim_scripts/clk_core/riviera/clk_core.udo
145103015/145103015.ip_user_files/sim_scripts/clk_core/riviera/compile.do
145103015/145103015.ip_user_files/sim_scripts/clk_core/riviera/file_info.txt
145103015/145103015.ip_user_files/sim_scripts/clk_core/riviera/glbl.v
145103015/145103015.ip_user_files/sim_scripts/clk_core/riviera/README.txt
145103015/145103015.ip_user_files/sim_scripts/clk_core/riviera/simulate.do
145103015/145103015.ip_user_files/sim_scripts/clk_core/riviera/wave.do
145103015/145103015.ip_user_files/sim_scripts/clk_core/vcs/clk_core.sh
145103015/145103015.ip_user_files/sim_scripts/clk_core/vcs/file_info.txt
145103015/145103015.ip_user_files/sim_scripts/clk_core/vcs/glbl.v
145103015/145103015.ip_user_files/sim_scripts/clk_core/vcs/README.txt
145103015/145103015.ip_user_files/sim_scripts/clk_core/vcs/simulate.do
145103015/145103015.ip_user_files/sim_scripts/clk_core/xsim/clk_core.sh
145103015/145103015.ip_user_files/sim_scripts/clk_core/xsim/cmd.tcl
145103015/145103015.ip_user_files/sim_scripts/clk_core/xsim/elab.opt
145103015/145103015.ip_user_files/sim_scripts/clk_core/xsim/file_info.txt
145103015/145103015.ip_user_files/sim_scripts/clk_core/xsim/glbl.v
145103015/145103015.ip_user_files/sim_scripts/clk_core/xsim/README.txt
145103015/145103015.ip_user_files/sim_scripts/clk_core/xsim/vhdl.prj
145103015/145103015.ip_user_files/sim_scripts/clk_core/xsim/vlog.prj
145103015/145103015.ip_user_files/sim_scripts/clk_core/xsim/xsim.ini
145103015/145103015.runs/.jobs/vrs_config_1.xml
145103015/145103015.runs/.jobs/vrs_config_10.xml
145103015/145103015.runs/.jobs/vrs_config_11.xml
145103015/145103015.runs/.jobs/vrs_config_12.xml
145103015/145103015.runs/.jobs/vrs_config_13.xml
145103015/145103015.runs/.jobs/vrs_config_2.xml
145103015/145103015.runs/.jobs/vrs_config_3.xml
145103015/145103015.runs/.jobs/vrs_config_4.xml
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