Lab1/SineRam.coe
Lab1/synth/
Lab1/synth/lab1/
Lab1/synth/lab1/_ngo/
Lab1/synth/lab1/_ngo/netlist.lst
Lab1/synth/lab1/_xmsgs/
Lab1/synth/lab1/_xmsgs/bitgen.xmsgs
Lab1/synth/lab1/_xmsgs/map.xmsgs
Lab1/synth/lab1/_xmsgs/ngdbuild.xmsgs
Lab1/synth/lab1/_xmsgs/par.xmsgs
Lab1/synth/lab1/_xmsgs/pn_parser.xmsgs
Lab1/synth/lab1/_xmsgs/trce.xmsgs
Lab1/synth/lab1/_xmsgs/xst.xmsgs
Lab1/synth/lab1/control_led.bgn
Lab1/synth/lab1/control_led.bit
Lab1/synth/lab1/control_LED.bld
Lab1/synth/lab1/control_LED.cmd_log
Lab1/synth/lab1/control_led.drc
Lab1/synth/lab1/control_LED.lso
Lab1/synth/lab1/control_LED.ncd
Lab1/synth/lab1/control_LED.ngc
Lab1/synth/lab1/control_LED.ngd
Lab1/synth/lab1/control_LED.ngr
Lab1/synth/lab1/control_LED.pad
Lab1/synth/lab1/control_LED.par
Lab1/synth/lab1/control_LED.pcf
Lab1/synth/lab1/control_LED.prj
Lab1/synth/lab1/control_LED.ptwx
Lab1/synth/lab1/control_LED.stx
Lab1/synth/lab1/control_LED.syr
Lab1/synth/lab1/control_LED.twr
Lab1/synth/lab1/control_LED.twx
Lab1/synth/lab1/control_LED.unroutes
Lab1/synth/lab1/control_LED.ut
Lab1/synth/lab1/control_LED.xpi
Lab1/synth/lab1/control_LED.xst
Lab1/synth/lab1/control_LED_bitgen.xwbt
Lab1/synth/lab1/control_LED_envsettings.html
Lab1/synth/lab1/control_LED_guide.ncd
Lab1/synth/lab1/control_LED_isim_beh.exe
Lab1/synth/lab1/control_LED_map.map
Lab1/synth/lab1/control_LED_map.mrp
Lab1/synth/lab1/control_LED_map.ncd
Lab1/synth/lab1/control_LED_map.ngm
Lab1/synth/lab1/control_LED_map.xrpt
Lab1/synth/lab1/control_LED_ngdbuild.xrpt
Lab1/synth/lab1/control_LED_pad.csv
Lab1/synth/lab1/control_LED_pad.txt
Lab1/synth/lab1/control_LED_par.xrpt
Lab1/synth/lab1/control_LED_summary.html
Lab1/synth/lab1/control_LED_summary.xml
Lab1/synth/lab1/control_LED_usage.xml
Lab1/synth/lab1/control_LED_xst.xrpt
Lab1/synth/lab1/fuse.log
Lab1/synth/lab1/fuse.xmsgs
Lab1/synth/lab1/fuseRelaunch.cmd
Lab1/synth/lab1/ipcore_dir/
Lab1/synth/lab1/ipcore_dir/_xmsgs/
Lab1/synth/lab1/ipcore_dir/_xmsgs/cg.xmsgs
Lab1/synth/lab1/ipcore_dir/_xmsgs/pn_parser.xmsgs
Lab1/synth/lab1/ipcore_dir/blk_mem_gen_ds512.pdf
Lab1/synth/lab1/ipcore_dir/blk_mem_gen_v6_3_readme.txt
Lab1/synth/lab1/ipcore_dir/coregen.cgp
Lab1/synth/lab1/ipcore_dir/coregen.log
Lab1/synth/lab1/ipcore_dir/create_sinlut.tcl
Lab1/synth/lab1/ipcore_dir/create_trilut.tcl
Lab1/synth/lab1/ipcore_dir/edit_sinlut.tcl
Lab1/synth/lab1/ipcore_dir/sinlut.asy
Lab1/synth/lab1/ipcore_dir/sinlut.gise
Lab1/synth/lab1/ipcore_dir/sinlut.mif
Lab1/synth/lab1/ipcore_dir/sinlut.ncf
Lab1/synth/lab1/ipcore_dir/sinlut.ngc
Lab1/synth/lab1/ipcore_dir/sinlut.sym
Lab1/synth/lab1/ipcore_dir/sinlut.v
Lab1/synth/lab1/ipcore_dir/sinlut.veo
Lab1/synth/lab1/ipcore_dir/sinlut.xco
Lab1/synth/lab1/ipcore_dir/sinlut.xise
Lab1/synth/lab1/ipcore_dir/sinlut/
Lab1/synth/lab1/ipcore_dir/sinlut/example_design/
Lab1/synth/lab1/ipcore_dir/sinlut/example_design/bmg_wrapper.vhd
Lab1/synth/lab1/ipcore_dir/sinlut/example_design/sinlut_top.ucf
Lab1/synth/lab1/ipcore_dir/sinlut/example_design/sinlut_top.vhd
Lab1/synth/lab1/ipcore_dir/sinlut/example_design/sinlut_top.xdc
Lab1/synth/lab1/ipcore_dir/sinlut/implement/
Lab1/synth/lab1/ipcore_dir/sinlut/implement/implement.bat
Lab1/synth/lab1/ipcore_dir/sinlut/implement/implement.sh
Lab1/synth/lab1/ipcore_dir/sinlut/implement/planAhead_rdn.bat
Lab1/synth/lab1/ipcore_dir/sinlut/implement/planAhead_rdn.sh
Lab1/synth/lab1/ipcore_dir/sinlut/implement/planAhead_rdn.tcl
Lab1/synth/lab1/ipcore_dir/sinlut/implement/xst.prj
Lab1/synth/lab1/ipcore_dir/sinlut/implement/xst.scr
Lab1/synth/lab1/ipcore_dir/sinlut/simulation/
Lab1/synth/lab1/ipcore_dir/sinlut/simulation/addr_gen.vhd
Lab1/synth/lab1/ipcore_dir/sinlut/simulation/bmg_stim_gen.vhd
Lab1/synth/lab1/ipcore_dir/sinlut/simulation/bmg_tb_pkg.vhd
Lab1/synth/lab1/ipcore_dir/sinlut/simulation/bmg_tb_synth.vhd
Lab1/synth/lab1/ipcore_dir/sinlut/simulation/bmg_tb_top.vhd
Lab1/synth/lab1/ipcore_dir/sinlut/simulation/checker.vhd
Lab1/synth/lab1/ipcore_dir/sinlut/simulation/data_gen.vhd
Lab1/synth/lab1/ipcore_dir/sinlut/simulation/functional/
Lab1/synth/lab1/ipcore_dir/sinlut/simulation/functional/isim_tcl_cmds.tcl
Lab1/synth/lab1/ipcore_dir/sinlut/simulation/functional/simulate_isim.bat
Lab1/synth/lab1/ipcore_dir/sinlut/simulation/functional/simulate_mti.do
Lab1/synth/lab1/ipcore_dir/sinlut/simulation/functional/simulate_ncsim.sh
Lab1/synth/lab1/ipcore_dir/sinlut/simulation/functional/wave_mti.do
Lab1/synth/lab1/ipcore_dir/sinlut/simulation/functional/wave_ncsim.sv
Lab1/synth/lab1/ipcore_dir/sinlut/simulation/random.vhd
Lab1/synth/lab1/ipcore_dir/sinlut/simulation/timing/
Lab1/synth/lab1/ipcore_dir/sinlut/simulation/timing/isim_tcl_cmds.tcl
Lab1/synth/lab1/ipcore_dir/sinlut/simulation/timing/simulate_isim.bat
Lab1/synth/lab1/ipcore_dir/sinlut/simulation/timing/simulate_mti.do
Lab1/synth/lab1/ipcore_dir/sinlut/simulation/timing/simulate_ncsim.sh
Lab1/synth/lab1/ipcore_dir/sinlut/simulation/timing/wave_mti.do
Lab1/synth/lab1/ipcore_dir/sinlut/simulation/timing/wave_ncsim.sv
Lab1/synth/lab1/ipcore_dir/sinlut_flist.txt
Lab1/synth/lab1/ipcore_dir/sinlut_xmdf.tcl
Lab1/synth/lab1/ipcore_dir/summary.log
Lab1/synth/lab1/ipcore_dir/tmp