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文件名称:VERILOG-Simulation

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2016-12-29
  • 文件大小：
    2.57mb
  • 已下载：
    0次
  • 提 供 者：
    R****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

This VERILOG simulation example shows a 16 bit group ripple adder circuit for FPGA. The netlabel is used to split 16 bit bus to four 4 bit bus and connect them to four 4 bit adder. The result is joined to a 16 bit bus using netlabel. The Simulation can be done in the built-in Aldec OEM simulator in Altium Designer.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

VERILOG Simulation/
VERILOG Simulation/16Bit Group Ripple Adder/
VERILOG Simulation/16Bit Group Ripple Adder/16Bit Group Ripple Adder.PrjFpg
VERILOG Simulation/16Bit Group Ripple Adder/16Bit Group Ripple Adder.PrjFpgStructure
VERILOG Simulation/16Bit Group Ripple Adder/16Bit Group Ripple Adder.SchDoc
VERILOG Simulation/16Bit Group Ripple Adder/TestBench.v
VERILOG Simulation/BCD Counter/
VERILOG Simulation/BCD Counter/BCD.v
VERILOG Simulation/BCD Counter/BCD8.PrjFpg
VERILOG Simulation/BCD Counter/BCD8.PrjFpgStructure
VERILOG Simulation/BCD Counter/BCD8.schdoc
VERILOG Simulation/BCD Counter/parity.v
VERILOG Simulation/BCD Counter/TestBench.v
VERILOG Simulation/Error Correcting For 7bit Hamming Code/
VERILOG Simulation/Error Correcting For 7bit Hamming Code/decoder.v
VERILOG Simulation/Error Correcting For 7bit Hamming Code/Error Correcting For 7bit Hamming Code.PrjFpg
VERILOG Simulation/Error Correcting For 7bit Hamming Code/Error Correcting For 7bit Hamming Code.PrjFpgStructure
VERILOG Simulation/Error Correcting For 7bit Hamming Code/Error Correcting For 7bit Hamming Code.SchDoc
VERILOG Simulation/Error Correcting For 7bit Hamming Code/parity.v
VERILOG Simulation/Error Correcting For 7bit Hamming Code/TestBench.v
VERILOG Simulation/Frequency Meter/
VERILOG Simulation/Frequency Meter/Control.SchDoc
VERILOG Simulation/Frequency Meter/Four Bit Decimal Counter ConfigCnt.SchDoc
VERILOG Simulation/Frequency Meter/Four Bit Decimal Counter.SchDoc
VERILOG Simulation/Frequency Meter/Four Decade BCD Counter.SchDoc
VERILOG Simulation/Frequency Meter/Frequency Meter.PrjFpg
VERILOG Simulation/Frequency Meter/Frequency Meter.PrjFpgStructure
VERILOG Simulation/Frequency Meter/Frequency Meter.SchDoc
VERILOG Simulation/Frequency Meter/hex7segment.v
VERILOG Simulation/Frequency Meter/TestBench.v
VERILOG Simulation/KeyBoard Reader/
VERILOG Simulation/KeyBoard Reader/KeyBrdReader.PrjFpg
VERILOG Simulation/KeyBoard Reader/KeyBrdReader.PrjFpgStructure
VERILOG Simulation/KeyBoard Reader/KeyBrdReader.SchDoc
VERILOG Simulation/KeyBoard Reader/TestBench.v
VERILOG Simulation/Parallel To Serial Converter/
VERILOG Simulation/Parallel To Serial Converter/Parallel To Serial Converter Bus.SchDoc
VERILOG Simulation/Parallel To Serial Converter/Parallel To Serial Converter.PrjFpg
VERILOG Simulation/Parallel To Serial Converter/Parallel To Serial Converter.PrjFpgStructure
VERILOG Simulation/Parallel To Serial Converter/Parallel To Serial Converter.SchDoc
VERILOG Simulation/Parallel To Serial Converter/shift_reg_bitblasted.v
VERILOG Simulation/Parallel To Serial Converter/TestBench.v
VERILOG Simulation/Pulse Width Modulation/
VERILOG Simulation/Pulse Width Modulation/pwm.PrjFpg
VERILOG Simulation/Pulse Width Modulation/pwm.PrjFpgStructure
VERILOG Simulation/Pulse Width Modulation/pwm.schdoc
VERILOG Simulation/Pulse Width Modulation/sch_pwm.schdoc
VERILOG Simulation/Pulse Width Modulation/TestBench.v
VERILOG Simulation/Serial To Parallel Converter/
VERILOG Simulation/Serial To Parallel Converter/Serial To Parallel Converter.PrjFpg
VERILOG Simulation/Serial To Parallel Converter/Serial To Parallel Converter.PrjFpgStructure
VERILOG Simulation/Serial To Parallel Converter/Serial To Parallel Converter.SchDoc
VERILOG Simulation/Serial To Parallel Converter/SR8CES.v
VERILOG Simulation/Serial To Parallel Converter/TestBench.v
VERILOG Simulation/Test BarLed Window/
VERILOG Simulation/Test BarLed Window/mux16.v
VERILOG Simulation/Test BarLed Window/TBarLedWindow.PRJFPG
VERILOG Simulation/Test BarLed Window/TBarLedWindow.PRJFPGStructure
VERILOG Simulation/Test BarLed Window/TBarLedWindow.schDOC
VERILOG Simulation/Test BarLed Window/TestBench.v
VERILOG Simulation/Test BarLed Window/TMouseEvent.schDoc
VERILOG Simulation/Test BarLed Window/TRange.v
VERILOG Simulation/Test BarLed Window/TWindow.schDoc
VERILOG Simulation/Test Control Window/
VERILOG Simulation/Test Control Window/JK_FF.v
VERILOG Simulation/Test Control Window/TControl.schDOC
VERILOG Simulation/Test Control Window/TControlWindow.PrjFpg
VERILOG Simulation/Test Control Window/TControlWindow.PrjFpgStructure
VERILOG Simulation/Test Control Window/TControlWindow.schDOC
VERILOG Simulation/Test Control Window/TestBench.v
VERILOG Simulation/Test Control Window/TMouseEvent.schDoc
VERILOG Simulation/Test Control Window/TRange.v
VERILOG Simulation/Test Control Window/TWindow.schDoc
VERILOG Simulation/Test Keyboard/
VERILOG Simulation/Test Keyboard/3to8bit_decoder_E.v
VERILOG Simulation/Test Keyboard/TestBench.v
VERILOG Simulation/Test Keyboard/Tkeyboard.PRJFPG
VERILOG Simulation/Test Keyboard/Tkeyboard.PRJFPGStructure
VERILOG Simulation/Test Keyboard/Tkeyboard.SchDoc
VERILOG Simulation/Test Palette Window/
VERILOG Simulation/Test Palette Window/TestBench.v
VERILOG Simulation/Test Palette Window/TMouseEvent.schDoc
VERILOG Simulation/Test Palette Window/TPaletteWindow.PrjFpg
VERILOG Simulation/Test Palette Window/TPaletteWindow.PrjFpgStructure
VERILOG Simulation/Test Palette Window/TPaletteWindow.schDOC
VERILOG Simulation/Test Palette Window/TRange.v
VERILOG Simulation/Test Palette Window/TWindow.schDoc
VERILOG Simulation/V

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