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文件名称:Area-Delay-Power-Efficient-Carry-Select-Adder-usi

  • 所属分类：
    Other systems
  • 标签属性：
    [ASM] [源码]
  • 上传时间：
    2017-03-03
  • 文件大小：
    595.9kb
  • 已下载：
    0次
  • 提 供 者：
    ana***
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

Implementation of IEEE 2015 paper for Area–Delay–Power Efficient Carry-Select Adder using VLSI verilog .The code tested by modelsim and also main program is test.v . If have any trouble mail to anandg.embedd@gmail.com-Implementation of IEEE 2015 paper for Area–Delay–Power Efficient Carry-Select Adder using VLSI verilog .The code tested by modelsim and also main program is test.v . If have any trouble　mail to anandg.embedd@gmail.com
(系统自动生成,下载前可以参看下载内容)

下载文件列表

Area–Delay–Power Efficient Carry-Select Adder using verilog/Area–Delay–Powerr.pdf
Area–Delay–Power Efficient Carry-Select Adder using verilog/Code/cg_0_2.v
Area–Delay–Power Efficient Carry-Select Adder using verilog/Code/cg_0_3.v
Area–Delay–Power Efficient Carry-Select Adder using verilog/Code/cg_0_4.v
Area–Delay–Power Efficient Carry-Select Adder using verilog/Code/cg_0_4.v.bak
Area–Delay–Power Efficient Carry-Select Adder using verilog/Code/cg_0_5.v
Area–Delay–Power Efficient Carry-Select Adder using verilog/Code/cg_0_5.v.bak
Area–Delay–Power Efficient Carry-Select Adder using verilog/Code/cg_1_2.v
Area–Delay–Power Efficient Carry-Select Adder using verilog/Code/cg_1_3.v
Area–Delay–Power Efficient Carry-Select Adder using verilog/Code/cg_1_3.v.bak
Area–Delay–Power Efficient Carry-Select Adder using verilog/Code/cg_1_4.v
Area–Delay–Power Efficient Carry-Select Adder using verilog/Code/cg_1_4.v.bak
Area–Delay–Power Efficient Carry-Select Adder using verilog/Code/cg_1_5.v
Area–Delay–Power Efficient Carry-Select Adder using verilog/Code/cg_1_5.v.bak
Area–Delay–Power Efficient Carry-Select Adder using verilog/Code/cs_2.v
Area–Delay–Power Efficient Carry-Select Adder using verilog/Code/cs_3.v
Area–Delay–Power Efficient Carry-Select Adder using verilog/Code/cs_4.v
Area–Delay–Power Efficient Carry-Select Adder using verilog/Code/cs_5.v
Area–Delay–Power Efficient Carry-Select Adder using verilog/Code/fsg_2.v
Area–Delay–Power Efficient Carry-Select Adder using verilog/Code/fsg_3.v
Area–Delay–Power Efficient Carry-Select Adder using verilog/Code/fsg_3.v.bak
Area–Delay–Power Efficient Carry-Select Adder using verilog/Code/fsg_4.v
Area–Delay–Power Efficient Carry-Select Adder using verilog/Code/fsg_4.v.bak
Area–Delay–Power Efficient Carry-Select Adder using verilog/Code/fsg_5.v
Area–Delay–Power Efficient Carry-Select Adder using verilog/Code/fsg_5.v.bak
Area–Delay–Power Efficient Carry-Select Adder using verilog/Code/full_adder.v
Area–Delay–Power Efficient Carry-Select Adder using verilog/Code/half_adder.v
Area–Delay–Power Efficient Carry-Select Adder using verilog/Code/hsg_2.v
Area–Delay–Power Efficient Carry-Select Adder using verilog/Code/hsg_3.v
Area–Delay–Power Efficient Carry-Select Adder using verilog/Code/hsg_4.v
Area–Delay–Power Efficient Carry-Select Adder using verilog/Code/hsg_5.v
Area–Delay–Power Efficient Carry-Select Adder using verilog/Code/modelsim.ini
Area–Delay–Power Efficient Carry-Select Adder using verilog/Code/rca.v
Area–Delay–Power Efficient Carry-Select Adder using verilog/Code/rca.v.bak
Area–Delay–Power Efficient Carry-Select Adder using verilog/Code/stage1.v
Area–Delay–Power Efficient Carry-Select Adder using verilog/Code/stage2.v
Area–Delay–Power Efficient Carry-Select Adder using verilog/Code/stage3.v
Area–Delay–Power Efficient Carry-Select Adder using verilog/Code/stage4.v
Area–Delay–Power Efficient Carry-Select Adder using verilog/Code/test.v
Area–Delay–Power Efficient Carry-Select Adder using verilog/Code/test.v.bak
Area–Delay–Power Efficient Carry-Select Adder using verilog/Code/vsim.wlf
Area–Delay–Power Efficient Carry-Select Adder using verilog/Code/work/cg_0_2/verilog.asm
Area–Delay–Power Efficient Carry-Select Adder using verilog/Code/work/cg_0_2/_primary.dat
Area–Delay–Power Efficient Carry-Select Adder using verilog/Code/work/cg_0_2/_primary.vhd
Area–Delay–Power Efficient Carry-Select Adder using verilog/Code/work/cg_0_3/verilog.asm
Area–Delay–Power Efficient Carry-Select Adder using verilog/Code/work/cg_0_3/_primary.dat
Area–Delay–Power Efficient Carry-Select Adder using verilog/Code/work/cg_0_3/_primary.vhd
Area–Delay–Power Efficient Carry-Select Adder using verilog/Code/work/cg_0_4/verilog.asm
Area–Delay–Power Efficient Carry-Select Adder using verilog/Code/work/cg_0_4/_primary.dat
Area–Delay–Power Efficient Carry-Select Adder using verilog/Code/work/cg_0_4/_primary.vhd
Area–Delay–Power Efficient Carry-Select Adder using verilog/Code/work/cg_0_5/verilog.asm
Area–Delay–Power Efficient Carry-Select Adder using verilog/Code/work/cg_0_5/_primary.dat
Area–Delay–Power Efficient Carry-Select Adder using verilog/Code/work/cg_0_5/_primary.vhd
Area–Delay–Power Efficient Carry-Select Adder using verilog/Code/work/cg_1_2/verilog.asm
Area–Delay–Power Efficient Carry-Select Adder using verilog/Code/work/cg_1_2/_primary.dat
Area–Delay–Power Efficient Carry-Select Adder using verilog/Code/work/cg_1_2/_primary.vhd
Area–Delay–Power Efficient Carry-Select Adder using verilog/Code/work/cg_1_3/verilog.asm
Area–Delay–Power Efficient Carry-Select Adder using verilog/Code/work/cg_1_3/_primary.dat
Area–Delay–Power Efficient Carry-Select Adder using verilog/Code/work/cg_1_3/_primary.vhd
Area–Delay–Power Efficient Carry-Select Adder using verilog/Code/work/cg_1_4/verilog.asm
Area–Delay–Power Efficient Carry-Select Adder using verilog/Code/work/cg_1_4/_primary.dat
Area–Delay–Power Efficient Carry-Select Adder using verilog/Code/work/cg_1_4/_primary.vhd
Area–Delay–Power Efficient Carry-Select Adder using verilog/Code/work/cg_1_5/verilog.asm
Area–Delay–Power Efficient Carry-Select Adder using verilog/Code/work/cg_1_5/_prima

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