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文件名称:project_2

  • 所属分类：
    VHDL/FPGA/Verilog
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2017-10-10
  • 文件大小：
    277kb
  • 已下载：
    0次
  • 提 供 者：
    yousi******
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

simple gates using ip integrator from xilinx
相关搜索： vivado

(系统自动生成,下载前可以参看下载内容)

下载文件列表

project_2
project_2\project_2.cache
project_2\project_2.cache\ip
project_2\project_2.cache\ip\2017.2
project_2\project_2.cache\ip\2017.2\5059e4fa596ef4c3
project_2\project_2.cache\ip\2017.2\5059e4fa596ef4c3.logs
project_2\project_2.cache\ip\2017.2\5059e4fa596ef4c3.logs\runme.log
project_2\project_2.cache\ip\2017.2\5059e4fa596ef4c3\5059e4fa596ef4c3.xci
project_2\project_2.cache\ip\2017.2\5059e4fa596ef4c3\AND_GATE_util_vector_logic_0_0.dcp
project_2\project_2.cache\ip\2017.2\5059e4fa596ef4c3\AND_GATE_util_vector_logic_0_0_sim_netlist.v
project_2\project_2.cache\ip\2017.2\5059e4fa596ef4c3\AND_GATE_util_vector_logic_0_0_sim_netlist.vhdl
project_2\project_2.cache\ip\2017.2\5059e4fa596ef4c3\AND_GATE_util_vector_logic_0_0_stub.v
project_2\project_2.cache\ip\2017.2\5059e4fa596ef4c3\AND_GATE_util_vector_logic_0_0_stub.vhdl
project_2\project_2.cache\ip\2017.2\5059e4fa596ef4c3\stats.txt
project_2\project_2.cache\ip\2017.2\f28d5379482a9529
project_2\project_2.cache\ip\2017.2\f28d5379482a9529.logs
project_2\project_2.cache\ip\2017.2\f28d5379482a9529.logs\runme.log
project_2\project_2.cache\ip\2017.2\f28d5379482a9529\AND_GATE_util_vector_logic_1_0.dcp
project_2\project_2.cache\ip\2017.2\f28d5379482a9529\AND_GATE_util_vector_logic_1_0_sim_netlist.v
project_2\project_2.cache\ip\2017.2\f28d5379482a9529\AND_GATE_util_vector_logic_1_0_sim_netlist.vhdl
project_2\project_2.cache\ip\2017.2\f28d5379482a9529\AND_GATE_util_vector_logic_1_0_stub.v
project_2\project_2.cache\ip\2017.2\f28d5379482a9529\AND_GATE_util_vector_logic_1_0_stub.vhdl
project_2\project_2.cache\ip\2017.2\f28d5379482a9529\f28d5379482a9529.xci
project_2\project_2.cache\wt
project_2\project_2.cache\wt\gui_resources.wdf
project_2\project_2.cache\wt\java_command_handlers.wdf
project_2\project_2.cache\wt\project.wpc
project_2\project_2.cache\wt\synthesis.wdf
project_2\project_2.cache\wt\synthesis_details.wdf
project_2\project_2.cache\wt\webtalk_pa.xml
project_2\project_2.cache\wt\xsim.wdf
project_2\project_2.hw
project_2\project_2.hw\project_2.lpr
project_2\project_2.ip_user_files
project_2\project_2.ip_user_files\bd
project_2\project_2.ip_user_files\bd\AND_GATE
project_2\project_2.ip_user_files\bd\AND_GATE\hdl
project_2\project_2.ip_user_files\bd\AND_GATE\hdl\AND_GATE.vhd
project_2\project_2.ip_user_files\bd\AND_GATE\ip
project_2\project_2.ip_user_files\bd\AND_GATE\ip\AND_GATE_util_vector_logic_0_0
project_2\project_2.ip_user_files\bd\AND_GATE\ip\AND_GATE_util_vector_logic_0_0\AND_GATE_util_vector_logic_0_0_sim_netlist.v
project_2\project_2.ip_user_files\bd\AND_GATE\ip\AND_GATE_util_vector_logic_0_0\AND_GATE_util_vector_logic_0_0_sim_netlist.vhdl
project_2\project_2.ip_user_files\bd\AND_GATE\ip\AND_GATE_util_vector_logic_0_0\sim
project_2\project_2.ip_user_files\bd\AND_GATE\ip\AND_GATE_util_vector_logic_0_0\sim\AND_GATE_util_vector_logic_0_0.v
project_2\project_2.ip_user_files\README.txt
project_2\project_2.runs
project_2\project_2.runs\.jobs
project_2\project_2.runs\.jobs\vrs_config_1.xml
project_2\project_2.runs\.jobs\vrs_config_2.xml
project_2\project_2.runs\AND_GATE_util_vector_logic_0_0_synth_1
project_2\project_2.runs\AND_GATE_util_vector_logic_0_0_synth_1\.vivado.begin.rst
project_2\project_2.runs\AND_GATE_util_vector_logic_0_0_synth_1\.vivado.end.rst
project_2\project_2.runs\AND_GATE_util_vector_logic_0_0_synth_1\.Vivado_Synthesis.queue.rst
project_2\project_2.runs\AND_GATE_util_vector_logic_0_0_synth_1\.Xil
project_2\project_2.runs\AND_GATE_util_vector_logic_0_0_synth_1\AND_GATE_util_vector_logic_0_0.dcp
project_2\project_2.runs\AND_GATE_util_vector_logic_0_0_synth_1\AND_GATE_util_vector_logic_0_0.tcl
project_2\project_2.runs\AND_GATE_util_vector_logic_0_0_synth_1\AND_GATE_util_vector_logic_0_0.vds
project_2\project_2.runs\AND_GATE_util_vector_logic_0_0_synth_1\AND_GATE_util_vector_logic_0_0_utilization_synth.pb
project_2\project_2.runs\AND_GATE_util_vector_logic_0_0_synth_1\AND_GATE_util_vector_logic_0_0_utilization_synth.rpt
project_2\project_2.runs\AND_GATE_util_vector_logic_0_0_synth_1\gen_run.xml
project_2\project_2.runs\AND_GATE_util_vector_logic_0_0_synth_1\htr.txt
project_2\project_2.runs\AND_GATE_util_vector_logic_0_0_synth_1\ISEWrap.js
project_2\project_2.runs\AND_GATE_util_vector_logic_0_0_synth_1\ISEWrap.sh
project_2\project_2.runs\AND_GATE_util_vector_logic_0_0_synth_1\rundef.js
project_2\project_2.runs\AND_GATE_util_vector_logic_0_0_synth_1\runme.bat
project_2\project_2.runs\AND_GATE_util_vector_logic_0_0_synth_1\runme.log
project_2\project_2.runs\AND_GATE_util_vector_logic_0_0_synth_1\runme.sh
project_2\project_2.runs\AND_GATE_util_vector_logic_0_0_synth_1\vivado.jou
project_2\project_2.runs\AND_GATE_util_vector_logic_0_0_synth_1\vivado.pb
project_2\project_2.runs\AND_GATE_util_vector_logic_1_0_synth_1
project_2\project_2.runs\AND_GATE_util_vector_logic_1_0_synth_1\.vivado.begin.rst
project_2\project_2.runs\AND_GATE_util_vector_logic_1_0_synth_1\.vivado.end.rst
project_2\project_2.runs\AND_GATE_util_vector_logic_1_0_synth_1\.Vivado_Synthesis.queue.rst
project_2\project_2.runs\AND_GATE_util_vector_logic_1_0_synth_1\.Xil
project_2\project_2.runs\AND_GATE_util_vector_logic_1_0_synth_1\AND_GATE_util_vector_logic_1_0.dcp
project_2\project_2.runs\AND_GATE_util_vector_logic_1_0_synth_1\AND_GATE_util_vector_logic_1_0.tcl
project_2\project_2.runs\AND_GATE_util_vector_logic_1_0_synth_1\AND_GATE_util_vector_logic_1_0.vds
project_2\project_2.runs\AND_GATE_util_vector_logic_1_0_synth_1\AND_GATE_util_vector_logic_1_0_utilization_synth.pb
project_2\project_2.runs\AND_GATE_util_vector_logic_1_0_synth_1\AND_GATE_util_vector_logic_1_0_utilization_synth.rpt
project_2\project_2.runs\AND_GATE_util_vector_logic_1_0_synth_1\gen_run.xml
project_2\project_2.runs\AND_GATE_util_vector_logic_1_0_synth_1\htr.txt
project_2\project_2.runs\AND_GATE_util_vector_logic_1_0_synth_1\ISEWrap.js
project_2\project_2.runs\AND_GATE_util_vector_logic_1_0_synth_1\ISEWrap.sh
project_2\project_2.runs\AND_GATE_util_vector_logic_1_0_synth_1\rundef.js
project_2\project_2.runs\AND_GATE_util_vector_logic_1_0_synth_1\runme.bat
project_2\project_2.runs\AND_GATE_util_vector_logic_1_0_synth_1\runme.log
project_2\project_2.runs\AND_GATE_util_vector_logic_1_0_synth_1\runme.sh
project_2\project_2.runs\AND_GATE_util_vector_logic_1_0_synth_1\vivado.jou
project_2\project_2.runs\AND_GATE_util_vector_logic_1_0_synth_1\vivado.pb
project_2\project_2.runs\synth_1
project_2\project_2.runs\synth_1\.vivado.begin.rst
project_2\project_2.runs\synth_1\.vivado.end.rst
project_2\project_2.runs\synth_1\.Vivado_Synthesis.queue.rst
project_2\project_2.runs\synth_1\.Xil
project_2\project_2.runs\synth_1\AND_GATE_wrapper.dcp
project_2\project_2.runs\synth_1\AND_GATE_wrapper.tcl
project_2\project_2.runs\synth_1\AND_GATE_wrapper.vds
project_2\project_2.runs\synth_1\AND_GATE_wrapper_utilization_synth.pb
project_2\project_2.runs\synth_1\AND_GATE_wrapper_utilization_synth.rpt
project_2\project_2.runs\synth_1\dont_touch.xdc

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