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文件名称:ref-sdr-sdram-vhdl
介绍说明－－下载内容来自于网络，使用问题请自行百度
DDR控制器的VHDL源代码.采用FPGA实现DDR接口控制器,适用于Altera的FPGA,最高频率可到100M-DDR controller VHDL source code. Using FPGA DDR interface controller, applicable to Altera FPGA, the highest frequency available 100M
(系统自动生成,下载前可以参看下载内容)
下载文件列表
CVS/
doc/
doc/CVS/
readme_sdr_sdram.txt
sdr_sdram.pdf
simulation/
simulation/CVS/
simulation/sdr_sdram_tb.vhd
source/
source/Command.vhd
source/control_interface.vhd
source/CVS/
source/pll1.vhd
source/sdr_data_path.vhd
source/sdr_sdram.vhd
doc/
doc/CVS/
readme_sdr_sdram.txt
sdr_sdram.pdf
simulation/
simulation/CVS/
simulation/sdr_sdram_tb.vhd
source/
source/Command.vhd
source/control_interface.vhd
source/CVS/
source/pll1.vhd
source/sdr_data_path.vhd
source/sdr_sdram.vhd
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