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文件名称:DPWM

  • 所属分类：
    VHDL/FPGA/Verilog
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2020-07-06
  • 文件大小：
    489kb
  • 已下载：
    1次
  • 提 供 者：
    lw1***
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

用Verilog实现数字脉宽调制模块，主要模块有锁相环、计数器、多路选择器(The digital pulse width modulation module is realized by Verilog. The main modules are PLL, counter and multiplexer)
相关搜索： verilog

(系统自动生成,下载前可以参看下载内容)

下载文件列表

文件名大小更新时间
DPWM 0 2020-05-12
DPWM\DPWM.cache 0 2020-04-23
DPWM\DPWM.cache\compile_simlib 0 2020-04-20
DPWM\DPWM.cache\compile_simlib\activehdl 0 2020-04-20
DPWM\DPWM.cache\compile_simlib\ies 0 2020-04-20
DPWM\DPWM.cache\compile_simlib\modelsim 0 2020-04-20
DPWM\DPWM.cache\compile_simlib\questa 0 2020-04-20
DPWM\DPWM.cache\compile_simlib\riviera 0 2020-04-20
DPWM\DPWM.cache\compile_simlib\vcs 0 2020-04-20
DPWM\DPWM.cache\compile_simlib\xcelium 0 2020-04-20
DPWM\DPWM.cache\ip 0 2020-04-20
DPWM\DPWM.cache\ip\2017.4 0 2020-04-20
DPWM\DPWM.cache\ip\2017.4\a25275f739195b31 0 2020-04-20
DPWM\DPWM.cache\ip\2017.4\a25275f739195b31.logs 0 2020-04-20
DPWM\DPWM.cache\ip\2017.4\a25275f739195b31.logs\runme.log 20358 2020-04-20
DPWM\DPWM.cache\ip\2017.4\a25275f739195b31\a25275f739195b31.xci 37946 2020-04-20
DPWM\DPWM.cache\ip\2017.4\a25275f739195b31\clk_wiz_0.dcp 9300 2020-04-20
DPWM\DPWM.cache\ip\2017.4\a25275f739195b31\clk_wiz_0_sim_netlist.v 6340 2020-04-20
DPWM\DPWM.cache\ip\2017.4\a25275f739195b31\clk_wiz_0_sim_netlist.vhdl 6232 2020-04-20
DPWM\DPWM.cache\ip\2017.4\a25275f739195b31\clk_wiz_0_stub.v 1419 2020-04-20
DPWM\DPWM.cache\ip\2017.4\a25275f739195b31\clk_wiz_0_stub.vhdl 1454 2020-04-20
DPWM\DPWM.cache\wt 0 2020-04-20
DPWM\DPWM.cache\wt\gui_handlers.wdf 6564 2020-04-23
DPWM\DPWM.cache\wt\java_command_handlers.wdf 1370 2020-04-23
DPWM\DPWM.cache\wt\project.wpc 61 2020-04-23
DPWM\DPWM.cache\wt\synthesis.wdf 5387 2020-04-20
DPWM\DPWM.cache\wt\webtalk_pa.xml 6056 2020-04-23
DPWM\DPWM.cache\wt\xsim.wdf 256 2020-04-21
DPWM\DPWM.hw 0 2020-04-23
DPWM\DPWM.hw\DPWM.lpr 290 2020-04-19
DPWM\DPWM.ip_user_files 0 2020-04-23
DPWM\DPWM.ip_user_files\ip 0 2020-04-20
DPWM\DPWM.ip_user_files\ip\clk_wiz_0 0 2020-04-21
DPWM\DPWM.ip_user_files\ip\clk_wiz_0\clk_wiz_0.veo 3988 2020-04-21
DPWM\DPWM.ip_user_files\ip\clk_wiz_0\clk_wiz_0_stub.v 1348 2020-04-20
DPWM\DPWM.ip_user_files\ip\clk_wiz_0\clk_wiz_0_stub.vhdl 1319 2020-04-20
DPWM\DPWM.ip_user_files\README.txt 130 2020-04-20
DPWM\DPWM.ip_user_files\sim_scripts 0 2020-04-20
DPWM\DPWM.ip_user_files\sim_scripts\clk_wiz_0 0 2020-04-20
DPWM\DPWM.ip_user_files\sim_scripts\clk_wiz_0\activehdl 0 2020-04-20
DPWM\DPWM.ip_user_files\sim_scripts\clk_wiz_0\activehdl\clk_wiz_0.sh 4966 2020-04-20
DPWM\DPWM.ip_user_files\sim_scripts\clk_wiz_0\activehdl\clk_wiz_0.udo 0 2020-04-20
DPWM\DPWM.ip_user_files\sim_scripts\clk_wiz_0\activehdl\compile.do 660 2020-04-20
DPWM\DPWM.ip_user_files\sim_scripts\clk_wiz_0\activehdl\file_info.txt 626 2020-04-20
DPWM\DPWM.ip_user_files\sim_scripts\clk_wiz_0\activehdl\glbl.v 1474 2017-12-14
DPWM\DPWM.ip_user_files\sim_scripts\clk_wiz_0\activehdl\README.txt 2181 2020-04-20
DPWM\DPWM.ip_user_files\sim_scripts\clk_wiz_0\activehdl\simulate.do 306 2020-04-20
DPWM\DPWM.ip_user_files\sim_scripts\clk_wiz_0\activehdl\wave.do 32 2020-04-20
DPWM\DPWM.ip_user_files\sim_scripts\clk_wiz_0\ies 0 2020-04-20
DPWM\DPWM.ip_user_files\sim_scripts\clk_wiz_0\ies\clk_wiz_0.sh 5723 2020-04-20
DPWM\DPWM.ip_user_files\sim_scripts\clk_wiz_0\ies\file_info.txt 662 2020-04-20
DPWM\DPWM.ip_user_files\sim_scripts\clk_wiz_0\ies\glbl.v 1474 2017-12-14
DPWM\DPWM.ip_user_files\sim_scripts\clk_wiz_0\ies\README.txt 2122 2020-04-20
DPWM\DPWM.ip_user_files\sim_scripts\clk_wiz_0\ies\run.f 440 2020-04-20
DPWM\DPWM.ip_user_files\sim_scripts\clk_wiz_0\modelsim 0 2020-04-20
DPWM\DPWM.ip_user_files\sim_scripts\clk_wiz_0\modelsim\clk_wiz_0.sh 5180 2020-04-20
DPWM\DPWM.ip_user_files\sim_scripts\clk_wiz_0\modelsim\clk_wiz_0.udo 0 2020-04-20
DPWM\DPWM.ip_user_files\sim_scripts\clk_wiz_0\modelsim\compile.do 725 2020-04-20
DPWM\DPWM.ip_user_files\sim_scripts\clk_wiz_0\modelsim\file_info.txt 626 2020-04-20
DPWM\DPWM.ip_user_files\sim_scripts\clk_wiz_0\modelsim\glbl.v 1474 2017-12-14
DPWM\DPWM.ip_user_files\sim_scripts\clk_wiz_0\modelsim\README.txt 2181 2020-04-20
DPWM\DPWM.ip_user_files\sim_scripts\clk_wiz_0\modelsim\simulate.do 311 2020-04-20
DPWM\DPWM.ip_user_files\sim_scripts\clk_wiz_0\modelsim\wave.do 32 2020-04-20
DPWM\DPWM.ip_user_files\sim_scripts\clk_wiz_0\questa 0 2020-04-20
DPWM\DPWM.ip_user_files\sim_scripts\clk_wiz_0\questa\clk_wiz_0.sh 5293 2020-04-20
DPWM\DPWM.ip_user_files\sim_scripts\clk_wiz_0\questa\clk_wiz_0.udo 0 2020-04-20
DPWM\DPWM.ip_user_files\sim_scripts\clk_wiz_0\questa\compile.do 701 2020-04-20
DPWM\DPWM.ip_user_files\sim_scripts\clk_wiz_0\questa\elaborate.do 183 2020-04-20
DPWM\DPWM.ip_user_files\sim_scripts\clk_wiz_0\questa\file_info.txt 626 2020-04-20
DPWM\DPWM.ip_user_files\sim_scripts\clk_wiz_0\questa\glbl.v 1474 2017-12-14
DPWM\DPWM.ip_user_files\sim_scripts\clk_wiz_0\questa\README.txt 2181 2020-04-20
DPWM\DPWM.ip_user_files\sim_scripts\clk_wiz_0\questa\simulate.do 195 2020-04-20
DPWM\DPWM.ip_user_files\sim_scripts\clk_wiz_0\questa\wave.do 32 2020-04-20
DPWM\DPWM.ip_user_files\sim_scripts\clk_wiz_0\README.txt 3236 2020-04-20
DPWM\DPWM.ip_user_files\sim_scripts\clk_wiz_0\riviera 0 2020-04-20
DPWM\DPWM.ip_user_files\sim_scripts\clk_wiz_0\riviera\clk_wiz_0.sh 4965 2020-04-20
DPWM\DPWM.ip_user_files\sim_scripts\clk_wiz_0\riviera\clk_wiz_0.udo 0 2020-04-20
DPWM\DPWM.ip_user_files\sim_scripts\clk_wiz_0\riviera\compile.do 650 2020-04-20
DPWM\DPWM.ip_user_files\sim_scripts\clk_wiz_0\riviera\file_info.txt 626 2020-04-20
DPWM\DPWM.ip_user_files\sim_scripts\clk_wiz_0\riviera\glbl.v 1474 2017-12-14
DPWM\DPWM.ip_user_files\sim_scripts\clk_wiz_0\riviera\README.txt 2181 2020-04-20
DPWM\DPWM.ip_user_files\sim_scripts\clk_wiz_0\riviera\simulate.do 306 2020-04-20
DPWM\DPWM.ip_user_files\sim_scripts\clk_wiz_0\riviera\wave.do 32 2020-04-20
DPWM\DPWM.ip_user_files\sim_scripts\clk_wiz_0\vcs 0 2020-04-20
DPWM\DPWM.ip_user_files\sim_scripts\clk_wiz_0\vcs\clk_wiz_0.sh 6999 2020-04-20
DPWM\DPWM.ip_user_files\sim_scripts\clk_wiz_0\vcs\file_info.txt 662 2020-04-20
DPWM\DPWM.ip_user_files\sim_scripts\clk_wiz_0\vcs\glbl.v 1474 2017-12-14
DPWM\DPWM.ip_user_files\sim_scripts\clk_wiz_0\vcs\README.txt 2181 2020-04-20
DPWM\DPWM.ip_user_files\sim_scripts\clk_wiz_0\vcs\simulate.do 11 2020-04-20
DPWM\DPWM.ip_user_files\sim_scripts\clk_wiz_0\xsim 0 2020-04-20
DPWM\DPWM.ip_user_files\sim_scripts\clk_wiz_0\xsim\clk_wiz_0.sh 6354 2020-04-20
DPWM\DPWM.ip_user_files\sim_scripts\clk_wiz_0\xsim\cmd.tcl 464 2020-04-20
DPWM\DPWM.ip_user_files\sim_scripts\clk_wiz_0\xsim\elab.opt 188 2020-04-20
DPWM\DPWM.ip_user_files\sim_scripts\clk_wiz_0\xsim\file_info.txt 364 2020-04-20
DPWM\DPWM.ip_user_files\sim_scripts\clk_wiz_0\xsim\glbl.v 1474 2017-12-14
DPWM\DPWM.ip_user_files\sim_scripts\clk_wiz_0\xsim\README.txt 2181 2020-04-20
DPWM\DPWM.ip_user_files\sim_scripts\clk_wiz_0\xsim\vlog.prj 233 2020-04-20
DPWM\DPWM.ip_user_files\sim_scripts\clk_wiz_0\xsim\xsim.ini 19045 2017-12-16
DPWM\DPWM.runs 0 2020-04-23
DPWM\DPWM.runs\.jobs 0 2020-04-20

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