Testbench/
Testbench/TB_mux_alu_b.v
Testbench/TB_alu_op_gen.v
Testbench/TB_alu_top.v
Testbench/TB_instruction_decoder.v
Testbench/TB_instruction_decoder_top.v
Testbench/TB_mux_alu_a.v
Testbench/TB_alu_op.v
Testbench/TB_pic16c5x.v
Testbench/TB_pic16c5x.v~
Testbench/TB_reg_fsr.v
Testbench/TB_reg_general.v
Testbench/TB_reg_top.v
source/
source/rom_7.dat
source/rom.dat
source/alu_op_gen.v
source/reg_general.v
source/alu_op.v
source/rom_8.dat
source/alu_top.v
source/rom_6.dat
source/rom_6_org.dat
source/instruction_decoder.v
source/instruction_decoder_top.v
source/instruction_reg.v
source/mux_alu_a.v
source/mux_alu_b.v
source/rom_1.dat
source/mux_fwe.v
source/pic16c5x.v
source/mux_status_write.v
source/program_counter.v
source/reg_fsr.v
source/reg_io.v
source/reg_mux_f.v
source/reg_status.v
source/reg_mux_w.v
source/reg_top.v
source/reg_w.v
pic16c5x.PDF
synthesis/
synthesis/exemplar.log
synthesis/pic16c5x_project.lsp
synthesis/pic16c5x_project.scr
synthesis/pic16c5x_project.xdb
synthesis/report