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文件名称:spimaster
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- 上传时间:2012-11-16
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文件大小:2.16mb
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SPI IP core supporting SD/MMC
(系统自动生成,下载前可以参看下载内容)
下载文件列表
spimaster/syn/spiMaster.qpf
spimaster/syn/spiMaster.qsf
spimaster/syn/CVS/Repository
spimaster/syn/CVS/Entries
spimaster/syn/CVS/Root
spimaster/syn/CVS
spimaster/syn
spimaster/sim/run_icarus.bat
spimaster/sim/build_icarus.bat
spimaster/sim/wave.do
spimaster/sim/run.do
spimaster/sim/compile.do
spimaster/sim/modelsim.ini
spimaster/sim/filelist.icarus
spimaster/sim/CVS/Repository
spimaster/sim/CVS/Entries
spimaster/sim/CVS/Root
spimaster/sim/CVS
spimaster/sim
spimaster/RTL/sm_fifoRTL.v
spimaster/RTL/initSD.v
spimaster/RTL/sm_TxFifo.v
spimaster/RTL/sm_TxFifoBI.v
spimaster/RTL/spiMasterWishBoneBI.v
spimaster/RTL/sm_dpMem_dc.v
spimaster/RTL/spiCtrl.v
spimaster/RTL/spiTxRxData.v
spimaster/RTL/sm_RxFifo.v
spimaster/RTL/readWriteSPIWireData.v
spimaster/RTL/readWriteSDBlock.v
spimaster/RTL/ctrlStsRegBI.v
spimaster/RTL/sm_RxFifoBI.v
spimaster/RTL/sendCmd.v
spimaster/RTL/spiMaster_defines.v
spimaster/RTL/spiMaster.v
spimaster/RTL/timescale.v
spimaster/RTL/CVS/Repository
spimaster/RTL/CVS/Entries
spimaster/RTL/CVS/Root
spimaster/RTL/CVS
spimaster/RTL
spimaster/doc/spiMaster_FSM.pdf
spimaster/doc/spiMaster_Specification.pdf
spimaster/doc/src/spiMaster_Specification.sxw
spimaster/doc/src/CVS/Repository
spimaster/doc/src/CVS/Entries
spimaster/doc/src/CVS/Root
spimaster/doc/src/CVS
spimaster/doc/src
spimaster/doc/CVS/Repository
spimaster/doc/CVS/Entries
spimaster/doc/CVS/Root
spimaster/doc/CVS
spimaster/doc
spimaster/model/wb_master_model.v
spimaster/model/sdModel.v
spimaster/model/CVS/Repository
spimaster/model/CVS/Entries
spimaster/model/CVS/Root
spimaster/model/CVS
spimaster/model
spimaster/CVS/Repository
spimaster/CVS/Entries
spimaster/CVS/Root
spimaster/CVS
spimaster/bench/testHarness.v
spimaster/bench/testCase0.v
spimaster/bench/CVS/Repository
spimaster/bench/CVS/Entries
spimaster/bench/CVS/Root
spimaster/bench/CVS
spimaster/bench
spimaster/Aldec/design0/design0.adf
spimaster/Aldec/design0/fsm.set
spimaster/Aldec/design0/src/readWriteSDBlock.asf
spimaster/Aldec/design0/src/spiCtrl.asf
spimaster/Aldec/design0/src/initSD.asf
spimaster/Aldec/design0/src/sendCmd.asf
spimaster/Aldec/design0/src/readWriteSPIWireData.asf
spimaster/Aldec/design0/src/CVS/Repository
spimaster/Aldec/design0/src/CVS/Entries
spimaster/Aldec/design0/src/CVS/Root
spimaster/Aldec/design0/src/CVS
spimaster/Aldec/design0/src
spimaster/Aldec/design0/log/CVS/Repository
spimaster/Aldec/design0/log/CVS/Entries
spimaster/Aldec/design0/log/CVS/Root
spimaster/Aldec/design0/log/CVS
spimaster/Aldec/design0/log
spimaster/Aldec/design0/compile/CVS/Repository
spimaster/Aldec/design0/compile/CVS/Entries
spimaster/Aldec/design0/compile/CVS/Root
spimaster/Aldec/design0/compile/CVS
spimaster/Aldec/design0/compile
spimaster/Aldec/design0/CVS/Repository
spimaster/Aldec/design0/CVS/Entries
spimaster/Aldec/design0/CVS/Root
spimaster/Aldec/design0/CVS
spimaster/Aldec/design0
spimaster/Aldec/CVS/Repository
spimaster/Aldec/CVS/Entries
spimaster/Aldec/CVS/Root
spimaster/Aldec/CVS
spimaster/Aldec
spimaster
spimaster/syn/spiMaster.qsf
spimaster/syn/CVS/Repository
spimaster/syn/CVS/Entries
spimaster/syn/CVS/Root
spimaster/syn/CVS
spimaster/syn
spimaster/sim/run_icarus.bat
spimaster/sim/build_icarus.bat
spimaster/sim/wave.do
spimaster/sim/run.do
spimaster/sim/compile.do
spimaster/sim/modelsim.ini
spimaster/sim/filelist.icarus
spimaster/sim/CVS/Repository
spimaster/sim/CVS/Entries
spimaster/sim/CVS/Root
spimaster/sim/CVS
spimaster/sim
spimaster/RTL/sm_fifoRTL.v
spimaster/RTL/initSD.v
spimaster/RTL/sm_TxFifo.v
spimaster/RTL/sm_TxFifoBI.v
spimaster/RTL/spiMasterWishBoneBI.v
spimaster/RTL/sm_dpMem_dc.v
spimaster/RTL/spiCtrl.v
spimaster/RTL/spiTxRxData.v
spimaster/RTL/sm_RxFifo.v
spimaster/RTL/readWriteSPIWireData.v
spimaster/RTL/readWriteSDBlock.v
spimaster/RTL/ctrlStsRegBI.v
spimaster/RTL/sm_RxFifoBI.v
spimaster/RTL/sendCmd.v
spimaster/RTL/spiMaster_defines.v
spimaster/RTL/spiMaster.v
spimaster/RTL/timescale.v
spimaster/RTL/CVS/Repository
spimaster/RTL/CVS/Entries
spimaster/RTL/CVS/Root
spimaster/RTL/CVS
spimaster/RTL
spimaster/doc/spiMaster_FSM.pdf
spimaster/doc/spiMaster_Specification.pdf
spimaster/doc/src/spiMaster_Specification.sxw
spimaster/doc/src/CVS/Repository
spimaster/doc/src/CVS/Entries
spimaster/doc/src/CVS/Root
spimaster/doc/src/CVS
spimaster/doc/src
spimaster/doc/CVS/Repository
spimaster/doc/CVS/Entries
spimaster/doc/CVS/Root
spimaster/doc/CVS
spimaster/doc
spimaster/model/wb_master_model.v
spimaster/model/sdModel.v
spimaster/model/CVS/Repository
spimaster/model/CVS/Entries
spimaster/model/CVS/Root
spimaster/model/CVS
spimaster/model
spimaster/CVS/Repository
spimaster/CVS/Entries
spimaster/CVS/Root
spimaster/CVS
spimaster/bench/testHarness.v
spimaster/bench/testCase0.v
spimaster/bench/CVS/Repository
spimaster/bench/CVS/Entries
spimaster/bench/CVS/Root
spimaster/bench/CVS
spimaster/bench
spimaster/Aldec/design0/design0.adf
spimaster/Aldec/design0/fsm.set
spimaster/Aldec/design0/src/readWriteSDBlock.asf
spimaster/Aldec/design0/src/spiCtrl.asf
spimaster/Aldec/design0/src/initSD.asf
spimaster/Aldec/design0/src/sendCmd.asf
spimaster/Aldec/design0/src/readWriteSPIWireData.asf
spimaster/Aldec/design0/src/CVS/Repository
spimaster/Aldec/design0/src/CVS/Entries
spimaster/Aldec/design0/src/CVS/Root
spimaster/Aldec/design0/src/CVS
spimaster/Aldec/design0/src
spimaster/Aldec/design0/log/CVS/Repository
spimaster/Aldec/design0/log/CVS/Entries
spimaster/Aldec/design0/log/CVS/Root
spimaster/Aldec/design0/log/CVS
spimaster/Aldec/design0/log
spimaster/Aldec/design0/compile/CVS/Repository
spimaster/Aldec/design0/compile/CVS/Entries
spimaster/Aldec/design0/compile/CVS/Root
spimaster/Aldec/design0/compile/CVS
spimaster/Aldec/design0/compile
spimaster/Aldec/design0/CVS/Repository
spimaster/Aldec/design0/CVS/Entries
spimaster/Aldec/design0/CVS/Root
spimaster/Aldec/design0/CVS
spimaster/Aldec/design0
spimaster/Aldec/CVS/Repository
spimaster/Aldec/CVS/Entries
spimaster/Aldec/CVS/Root
spimaster/Aldec/CVS
spimaster/Aldec
spimaster
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