74hc283.pdf
74hc283/
74hc283/74hc238.prj
74hc283/component/
74hc283/constraint/
74hc283/coreconsole/
74hc283/designer/
74hc283/designer/impl1/
74hc283/designer/impl1/adder4.adb
74hc283/designer/impl1/adder4.dtf/
74hc283/designer/impl1/adder4.dtf/verify.log
74hc283/designer/impl1/adder4.ide_des
74hc283/designer/impl1/adder4.pdb
74hc283/designer/impl1/adder4.pdb.depends
74hc283/designer/impl1/adder4.tcl
74hc283/designer/impl1/adder4_fp/
74hc283/designer/impl1/adder4_fp/$$FlashPro_07294.L$$
74hc283/designer/impl1/adder4_fp/adder4.log
74hc283/designer/impl1/adder4_fp/adder4.pro
74hc283/designer/impl1/adder4_fp/projectData/
74hc283/designer/impl1/adder4_fp/projectData/adder4.pdb
74hc283/designer/impl1/designer.log
74hc283/designer/impl1/simulation/
74hc283/hdl/
74hc283/hdl/74hc238.v
74hc283/phy_synthesis/
74hc283/simulation/
74hc283/simulation/modelsim.ini
74hc283/simulation/modelsim.log
74hc283/simulation/presynth/
74hc283/simulation/presynth/adder4/
74hc283/simulation/presynth/adder4/verilog.psm
74hc283/simulation/presynth/adder4/_primary.dat
74hc283/simulation/presynth/adder4/_primary.dbs
74hc283/simulation/presynth/adder4/_primary.vhd
74hc283/simulation/presynth/testbench/
74hc283/simulation/presynth/testbench/verilog.psm
74hc283/simulation/presynth/testbench/_primary.dat
74hc283/simulation/presynth/testbench/_primary.dbs
74hc283/simulation/presynth/testbench/_primary.vhd
74hc283/simulation/presynth/_info
74hc283/simulation/presynth/_temp/
74hc283/simulation/presynth/_vmake
74hc283/simulation/run.do
74hc283/simulation/vsim.wlf
74hc283/smartgen/
74hc283/smartgen/smartgen.aws
74hc283/stimulus/
74hc283/stimulus/testbench.v
74hc283/synthesis/
74hc283/synthesis/adder4.areasrr
74hc283/synthesis/adder4.edn
74hc283/synthesis/adder4.fse
74hc283/synthesis/adder4.htm
74hc283/synthesis/adder4.map
74hc283/synthesis/adder4.pdc
74hc283/synthesis/adder4.sap
74hc283/synthesis/adder4.sdf
74hc283/synthesis/adder4.so
74hc283/synthesis/adder4.srd
74hc283/synthesis/adder4.srm
74hc283/synthesis/adder4.srr
74hc283/synthesis/adder4.srs
74hc283/synthesis/adder4.szr
74hc283/synthesis/adder4.tlg
74hc283/synthesis/adder4_sdc.sdc
74hc283/synthesis/adder4_syn.prj
74hc283/synthesis/backup/
74hc283/synthesis/coreip/
74hc283/synthesis/run_options.txt
74hc283/synthesis/stdout.log
74hc283/synthesis/syntmp/
74hc283/synthesis/syntmp/adder4.plg
74hc283/synthesis/syntmp/adder4_flink.htm
74hc283/synthesis/syntmp/adder4_srr.htm
74hc283/synthesis/syntmp/adder4_toc.htm
74hc283/synthesis/syntmp/sap.log
74hc283/viewdraw/
74hc283/viewdraw/sch/
74hc283/viewdraw/sym/
74hc283/viewdraw/vf/
74hc283/viewdraw/vf/project.lst
74hc283/viewdraw/viewdraw.ini
74hc283/viewdraw/wir/