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VS1003
- VS1003音频解码芯片为VS10XX系列的第三代产品，是芬兰VLSI Solution Oy公司生产的单片MP3/WMA/MIDI解码和ADPCM编码芯片，它内部包含一个高性能、低功耗的DSP处理核（VSDSP），一个工作内存，一片可供用户程序使用的5.5KB RAM，一个串行SPI总线接口，一个高质量的采样频率可调的过采样DAC以及一个16位的采样ADC.-VS1003 Audio Decoder Chip for VS10XX series of the third-generation
CPLD
- This paper presents a low-power asynchronous implementation of the 80C51 microcontroller. It was realized in a 0.5 µ m CMOS process and it shows a power advantage of a factor 4 compared to a recent synchronous implementation in the same technolo
seminar040227
- Low Power VLSI Design For Multimedia Applications
-Elliptic
- We present elliptic curve cryptography (ECC) coprocessor, which is dual-field processor with projective coordinator. We have implemented architecture for scalar multiplication, which is key operation in elliptic curve cryptography. Our coproc
51nrf905
- nRF905 是挪威 Nordic VLSI 公司推出的单片射频收发器，工作电压为 1.9 ～3.6V， 32 引脚 QFN 封装 (5×5mm)，工作于 433/868/915MHz 三个 ISM(工业、科学和医学)频道，频道之间的转换时间小于 650us。 nRF905 由频率合成器、接收解调器、功率放大器、晶体振荡器和调制器组成，不需外加声表滤波器， ShockBurstTM 工作模式，自动处理字头和 CRC(循环冗余码校验)，使用 SPI 接口与微控制器通信，配置非 常方便。此外，
low-ref
- LOW POWER REFERENCE PAPER FOR VLSI DESIGN
bist 2017 paper
- A new low-power (LP) scan-based built-in selftest (BIST) technique is proposed based on weighted pseudorandom test pattern generation and reseeding. A new LP scan architecture is proposed, which supports both pseudorandom testing and deterministi
Low-Power CMOS Acquisition
- A low-power analog acquisition front-end circuit for Wireless Body Area Network (WBAN).
jeas_reversable-vedic-multiplier
- reversible logic is mainly used to achieve low power. peres gate HUG gate is used to design a vedic multiplier. reversible gate we can give n numbers of input and we can get n number of output
LOW POWER VLSI REPORT - SHORT CIRCUIT POWER
- short circuit power analysis of inverter for different rise time, fall time and capacitor value as simulated in Tanner tool.