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ALU.zip
- VHDL实现cpu核心逻辑与运算单元模块的实现，完成4bit*4bit输入8bit输出的运算，可做加减乘除逻辑移位6种操作,the implementation of Arithmetic and logic unit based on VHDL, can do as the adder,subtractor,multiplier,divider,shifter and logic operation.
minus
- 一位二进制全减器的设计，分别用原理图输入法和文本输入法，用分层设计的方法完成-A binary full subtractor design, respectively, schematic input and text input method, complete with a hierarchical design method
vhdl_123
- 几个简单的vhdl程序。包括加法器，减法器，乘除法等等。-A few simple vhdl program. Including the adder, subtractor, multiplication and division and so on.
AdderSubtractor
- 4-Bit Adder Subtractor Verilog Code. (Complete project)
vhdl5
- program for half subtractor.
addersandsubtractors
- this project is based on half adder ,full adder,half subtractor and full subtractor using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code c
HA
- Verilog HDL for Half Adder, Full Subtractor, Half Subtractor and 2x4 decoder.
addersubtractor10
- vhdl coding for adder subtractor used in dct
fft
- this subtractor. for developing the fft transforms. here i am developing the source for the fft. -this is subtractor. for developing the fft transforms. here i am developing the source for the fft.
VerilogSourceCode
- 乘法器、除法器、多路选择器、编码器、BCD码转换、加法器、减法器、状态机、四位比较器、数码管、串口、跑马灯、电子钟-Multiplier, divider, multiplexer, encoder, BCD code converter, adder, subtractor, state machines, four more players, digital control, serial port, marquees, electronic clock
subtractor
- Verilog source code for full subtractor module build with predefined nor gates.
subtractor2
- Verilog full subtractor module and tests build with a half subtractor made with predefined nand gates.
subtractor3
- Verilog 3bit full subtractor module and tests build with predefined nor gates.
subtractor4
- Verilog half subtractor module and tests build with made with gates built with expression modules.
Advanced_Adders
- Advanced topic on adders including: Carry Look Ahead Adder, Binary Parallel Adder/Subtractor, BCD adder circuit, Binary mutiplier circuit.
sm
- This example shows how a Sm component is directly coded in VHDL as concurrent statements. The multiplexor is coded as a single "when" statement. "Sm" is mnemonic for subtractor-multiplexor.
VHDL-CODE-for-adder-and-subtractor
- vhdl code for implementation of adder and subtractor on fpga
VHDL-Code-For-Full-Subtractor-By-Data-Flow-Modell
- VHDL Code For Full Subtractor By Data Flow Modelling
VHDL-Code-For-Half-Subtractor-By-Data-Flow-Modell
- VHDL Code For Half Subtractor By Data Flow Modelling
floating-point-adder-subtractor
- floating point adder/subtractor in VHDL