搜索资源列表
jiafaqi
- 实现四位加法器的VHDL代码，里面含有全加器的代码-achieve four Adder VHDL code, which contains the full adder code
ADDER4B
- 此程序是用VHDL硬件描述语言编写的,实现四位全加器的功能-This procedure is used VHDL hardware descr iption languages, the realization of the four full-adder function
testZ
- 八位加法器的原理图实现方法和一位半加器 全加器的原理图实现-Eight adder schematic diagram of the method and a half adder full adder schematic diagram of the realization of
add4bit
- 一位全加器的VHDL源码与TEST BENCH.XILINX下通过-A full adder and the VHDL source code through TEST BENCH.XILINX
full_aller
- 这是基于VHDL的一位全加器设计的程序，分析过程全面-This is based on a full adder VHDL design process, a comprehensive analysis process
sy1_yt
- 在max-plus 环境下使用vhdl语言实现用半加器组成全加器的功能。-In the max-plus environment, using vhdl language component with half adder full adder function.
fadd16
- 实验用16位全加器的VHDL代码，适合初学者学习，数电学习的好工具。 -Experiment with 16-bit full adder VHDL code for beginners to learn, a good tool to learn a few power.
Full-Adder
- 用VHDL实现的全加器，采用dataflow style编写，是学习VHDL入门级的好范例. 包括主程序和测试程序-Full adder by using VHDL, dataflow style writing. It is a good example of VHDL especially for the entry-level leaner（Testbench included）
Full_Adder_2
- 利用VHDL实现的全加器的第二种code。采用behavioral 风格编写，可以很帮助学习者区分两种语言风格（与Full adder--dataflow比较）-The second full adder is also designed by using VHDL，behavioral style of writing. It can help learners distinguish between the two language style (Please compare with "F
89_full_adder
- 全加器。VHDL入门例程。3个源程序。好好练习啊-Full adder. Introduction to VHDL routines. 3 source. Ah good practice
or2a
- 使用vhdl语言设计一位全加器，在仪器上下载并实现LED灯的闪亮-A full adder design
qjq
- 基于VHDL的全加器程序，用门电路实现两个二进数相加并求出和的组合线路，就是求二进制数矢量加法的。-Full adder VHDL-based program, with gates to achieve two binary numbers together and find a combination of lines and is seeking the binary vector addition.
jiafaqi
- 一位全加器的VHDL程序，上学时实验用的，很简单的，初学者可以-A full adder VHDL program, school experiment, very simple, beginners can look
adder2
- 全加器的VHDL数据流描述，提供VHDL代码 可以用Quartus 和MAX PLUS-full adder
Design-of-full-adder
- 熟悉VHDL元件例化语句的作用 熟悉全加器的工作原理 用VHDL语言设计一位二进制全加器，并仿真。-The role of components instantiated. Familiar with VHDL statements Familiar with the working principle of full adder Using VHDL language to design a binary full adder, and simulation.
adder
- 全加器：Powerpoint课件示例支持，典型组合逻辑原理图输入设计-full adder design with VHDL
1
- 用VHDL语言设计全加器的设计方法，使用元件例化的方法设计多位加法器-VHDL language design full adder design method using component instantiation approach to design multi-bit adder
fulladder
- 一位全加器的设计，基于VHDL语言的，顶层为语言-full adder
xor4b
- 实现四位全加器，为初学者提供参考说明，对VHDL语言有一定了解(it's a addler of four bits,which is designed for the new learner of VHDL language)
xor8b
- 实现8位全加器，为初学者提供参考，对VHDL语言有一定了解(It's a addler of 8 bits,which is designed for new learners)