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fwrememorybistvcestudent
- bist method for simulation of micro controller
BISTProject
- BIST test doing project, in verilog.
A-compact-AES-core-with-on-line-error-detection-f
- This paper presents a compact, low-cost, on-line error-detection architecture for a 32-bit hardware implementation of the AES. The implemented AES is specially designed for FPGA-based embedded applications, since it is tuned to specific FPGA logi
zc706-bist-rdf0240-14.5-c
- 入手zc706开发板必备文件包，作为开发板的第一个工程(Start with the zc706 development board essential file package, as the development board of the first project)
jeas_reversable-vedic-multiplier
- reversible logic is mainly used to achieve low power. peres gate HUG gate is used to design a vedic multiplier. reversible gate we can give n numbers of input and we can get n number of output
ahb_sramc
- 基于AHB总线的sram控制器，带有memory bist(SRAM controller based on AHB bus)