利用verilog语言设计32位进位选择加法器。实现高速计算功能。-Use verilog language design 32 carry select adder. High-speed computing.

Implementation of IEEE 2015 paper for Area–Delay–Power Efficient Carry-Select Adder using VLSI verilog .The code tested by modelsim and also main program is test.v . If have any trouble mail to anandg.embedd@gmail.com-Implementation of IEEE 2015 pape

IT IS A CARRY S ELECT ADDER TO IMPROVE PERFORMANCE.