搜索资源列表
apb_slave
- AMBA 2.0 APB Example- SRAM -AMBA 2.0 APB Example- SRAM
sc_apbSlave
- systemc写的apb slave程序，用于实现apb总线上的slave-systemc write apb slave procedure used to implement apb bus slave
RTC
- verilog编写的RTC（实时时钟）包含APB总线接口、时钟计时部分等-verilog prepared by the RTC (real time clock) contains APB bus interface, clock time some other
AHBPAPB
- AMBA总线的AHB+APB源程序，供初学者学习。-Verilog for AHB and APB
apb_bridge
- AMBA AHB总线上连接慢速设备的slave,通过 apb_bridge桥实现AHB到APB的转换-AMBA apb_bridge
aPb
- 运算a+b的小程序，输入a+b，输出其值.-Computing a+b applet, enter a+b, output its value.
APB
- 用C++语言实现计算两个大整型数据的和。-Calculate two big integers and
lab1
- apb transactions with DUT, testbench including interface test cases , top
AMBA-Bus_Verilog_Model
- AMBA-Bus_Verilog_Model with ahb and apb
Lec-7-APB-CaseStudy
- AMBA-APB Case Study, Testing & Verification
APB
- ACM A+B ID1001源代码实现程序-ACM A+B ID1001
apb_dut
- it is a verilog code for the apb slave dut
aPb
- 题目描述 给出两个非负实数a和b，求a+b 输入 一组用例，包括两个长度不大于400的非负实数a和b 输出 输出一行为a+b的最简形式，即没有前置0后置0，小数部分为0则省略小数点 样例输入 1 1 样例输出 2-Title Descr iption Two non negative real numbers a and B are given, and the a+b is obtai
High-precision-APB-Problem
- High precision A + B Problem，解除内存的问题-High precision A+ B Problem
apb
- Verilog code for APB Protocol
apb_timer
- Verilog code of timer for APB
ahb2apb-master
- ahb to apb master and slave
ahb2apb_bridge_verification-master
- ahb to apb master verification
apb_uart_sv-pulpinov1
- SystemVerilog 写的APB总线接口的uart 代码，带testbench.(Uart code of APB bus interface written by SystemVerilog, with testbench.)
APB_timer
- 设计一个挂载在 APB 总线上的计数器，按照 APB 的时序给计数器赋值，主 机通过地址对计数器进行配置，通过数据输入端口给计数器设置计数器最大值， 并通过数据输出端口输出计数器的计数值。该设计还设置了一个计数完成信号， 当计数器满足模式配置后的计数要求时，会将该信号拉高(A counter mounted on the APB bus is designed. The counter is assigned according to the sequence of APB The compu