搜索资源列表
amba3core.rar
- amba3 sva 完全验证的代码，有verilog的和systemverilog的,amba3 sva fully validate the code, and the Verilog and SystemVerilog
ahb2ahb.rar
- AMBA总线AHB TO AHB bridge,AMBA bus AHB TO AHB bridge
apb_slave
- AMBA 2.0 APB Example- SRAM -AMBA 2.0 APB Example- SRAM
AHBPAPB
- AMBA总线的AHB+APB源程序，供初学者学习。-Verilog for AHB and APB
AMBA
- AMBA总线的verilog实现，AMBA是ARM limited 公司推出的一种为嵌入式系统所设计的总线协议。-AMBA bus Verilog, AMBA bus protocol is the the of ARM limited company launched a embedded system design.
apb_bridge
- AMBA AHB总线上连接慢速设备的slave,通过 apb_bridge桥实现AHB到APB的转换-AMBA apb_bridge
AMBA-Bus_Verilog_Model
- AMBA-Bus_Verilog_Model with ahb and apb
AHB_Slave.v
- AMBA AHB PROTOCOL fsdfs
Lec-7-APB-CaseStudy
- AMBA-APB Case Study, Testing & Verification
rtl
- amba apb3.0 的桥代码，经过验证，完全正确-amba apb3.0 bridge code, proven completely correct
bus_ahb_to_sram
- amba ahb to sram verilog
ahb_fsm
- AMBA AHB design code.rar
AXI4与AXI3的区别
- AXI4与AXI3的区别,l例如：AXI4对burst length进行了扩展：AXI3最大burst length是16 beats,而AXI4支持最大到256 beats，但是仅支持INCR burst type超过16 beats，exclusive access也不能超过16beats;。(the different of AXI4 and AXI3)
CoreAMBA_BFM_UG
- 用AMBA主从功能仿真的指令详细描述，非常简单。(CORETEX-M3 AMBA BFM simulation)
AHB
- 基于amba总线协议中的ahb总线的从机模块代码,需要modelsim进行测试仿真(Based on the slave bus module code of AHB bus in AMBA bus protocol, Modelsim is needed to carry out test simulation.)
AMBA-AXI3-master (1)
- AXI4 verification and design using verilog.