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PCI_VHDL
- 从PCI时序分析入手，重点阐述了PCI通用的状态机设计，说明了用VHDL语言来实现本PIC通信状态机的软件设计以及进行MaxPlusII验证的程序和方法。用该方法所设计的接口既可支持PCI常规传输，又可支持PCI猝发传输。-PCI timing analysis from the start, focusing on general-purpose PCI state machine design, described by VHDL language to achieve the PIC c
vhdl_digital_output
- Digital signal output module... tested by Altera MaxPlusII or Quatus -Digital signal output module... tested by Altera MaxPlusII or Quatus II
vhdl_edge_ris
- rise edge detecting some signal module... tested by Altera MaxPlusII or Quatus -rise edge detecting some signal module... tested by Altera MaxPlusII or Quatus II
vhdl_i2c_slave
- Inter Intergrate Circuit slave module... tested by Altera MaxPlusII or Quatus -Inter Intergrate Circuit slave module... tested by Altera MaxPlusII or Quatus II
vhdl_pwm_drv
- Pulse Width Modulation signal generation output module... tested by Altera MaxPlusII or Quatus -Pulse Width Modulation signal generation output module... tested by Altera MaxPlusII or Quatus II
vhdl_sram_ctrl
- Sycronous SRAM in CPLD or FPGA module... tested by Altera MaxPlusII or Quatus -Sycronous SRAM in CPLD or FPGA module... tested by Altera MaxPlusII or Quatus II
diver
- 利用VHDL语言设计了五位除法器 实验环境为maxplusII 内有各个模块详细的程序代码 以及相应的模块截图-Designed using VHDL, five divider within the experimental environment maxplusII detailed code of each module and the corresponding module screenshot
MaxPPlus-II
- maxplusII教程 Max+Plus II 简易用户使 用入门指南-maxplusII teaching material Simple user use portal guide
dianzhenhanzi
- 用VHDL语言实现汉字点阵的动态循环显示，同时有视频可以教大家使用MAXPLUSII。-Implemented in VHDL language character dot-matrix display dynamic cycle, while the video can teach you to use MAXPLUSII.