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- 在max_plus2和FPGA实验箱上实现频率计的功能，原创-In the experimental box max_plus2 and FPGA to achieve the function of the frequency of the original
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- 用于电信相关专业学生的电子设计，本代码是由VHDL编写的，包括全套的内容。-Students for the telecom-related electronic design, the code is written by VHDL, including a full range of content.
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- 基于VHDL的数字频率计的设计-VHDL-based design of digital frequency meter
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- 能够较准确的测量1到65535之间的频率，希望对大家有所帮助-To a more accurate measurement of the frequency of between 1 to 65535, we want to help
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- 频率计 AD0832输出想要的频率 自己设计的仅供参考-Frequency meter AD0832 output frequency
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- 一个用verilog编写的数字频率计，利用FPGA实现计数功能，其中使用的测周法。-A written with verilog digital frequency meter, use FPGA implementation counting function, wherein the measured circumference method to use.
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- 利用单片机的内部定时器溢出产生中断来实现定时， 把单片机内部的定时/计数器0作为定时器，实现2.5ms定时。外部待测脉冲从单片机的TI（第15引脚）输入，以定时/计数器1作为计数器，利用中断方式来达到间接测量的目的。最后采用四位数码管显示-The use of MCU internal timer overflow interrupt to achieve timing, the MCU internal timer/counter 0 as a timer, the timing to a
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- 4位十进制频率计：根据testmode值的4种情况分别进行分频，即设置了mode模块产生4种情况；通过1Hz分频与flag_1s的状态机模块产生一个持续1s的高电平信号，再用freq_count对测试信号进行计数-4 decimal frequency meter：According to the testmode value of the four cases were divided, that is set up the mode module to produce four cases
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- 基于AT89C51+MAX7219的频率计 附带proteus仿真电路图 实际硬件电路测试通过- U57FA u4E8EAT89C51+MAX7219 u7684 u9891 u7397 u8641 u9644 u5E26proteus u4EFF u771F u7535 u8DEF u56FE u5B9E u9645 u786C u4EF6 u7535 u8DEF u6D4B u8BD5 u901A u8FC7