搜索资源列表
vhdl
- VHDL 的一个流水灯程序 开发平台Quartusii 使用的延时方法为分频思想
8.1
- ALTERA quartusii 破解 -quartusii
lcd1602-verilog
- 基于QuartusII的LCD1602-Verilog 源代码，可以直接应用于FPGA开发板。-QuartusII based on the LCD1602-Verilog source code, can be directly applied to FPGA development board.
adder4
- 四位加法器，适合初学者学习使用，包括实验要求，四位加法器程序代码，QuartusII功能仿真后的波形图。-Four adder, suitable for beginners learning to use, including the experimental requirements, the four code adder, QuartusII functional simulation of the wave after.
Crack_patch_license
- Quartus II 6.0 破解补丁和license设置-Quartus II 6.0 crack patch and license settings
exer1
- 作为基于FPGA的QuartusII平台上验证成功的LED灯程序的FPGA实现（VHDL）-As FPGA-based platform QuartusII LED lights proved to be successful FPGA implementation process (VHDL)
usb-blaster
- altera quartusII usb byteblaster转接板原理图以及相应源码-altera quartusII usb byteblaster adapter board schematic and the corresponding source
viterbi_encoding_213
- Viterbi213编码程序的VHDL的实现，包括整个quartusII 的工程文件，以及仿真波形图-Viterbi213 VHDL code implementation of procedures, including the quartusII project files, and simulation waveforms
viterbi213
- 编码方式为213的Viterbi卷积码编码器和译码器的FPGA的实现，包含整个QuartusＩＩ的工程文件，解码方式为寄存器交换法-Encoding for the 213 convolutional code encoder and Viterbi decoder FPGA realization of the project file that contains the entire QuartusII, decoding method for the register exchange
PipelineCPU
- Quartus II 7.2环境中，采用硬件描述语言VHDL独立完成了基于MIPS指令集的32位RISC处理器的逻辑设计-quartusII mips pipeline 32bit cpu design
quartusII
- qautusII官方中文使用手册，非常实用！-qautusII official English manual, very useful!
quartus2
- quartusII实用指南，对了解和学习quartusII很有帮助的。 -quartusII practical guide to understanding and learning quartusII helpful.
QuartusII
- 最详细的QuartusII中文教程，非常全面，值得下载参考，供学生和工程技术人员使用！-Chinese QuartusII most detailed tutorial, very comprehensive, it is worth to download information for students and engineers to use!
Count_30
- 篮球比赛三十秒计数器，在quartusII上进行设计的-Basketball game thirty seconds counter
Example-b4-1
- 利用quartusII开发软件的宏功能模块调用功能，定制了一个双端口RAM。-Utilize quartusII development software macro function module calls a function to customize a dual-port RAM.
single-clock-CPU
- 单时钟周期CPU，verilog语言编写，quartusII运行-A single clock cycle CPU
Div
- 非常好用的小数除法器，verilog开发的。quartusii下综合通过-Very easy to use fractional divider, verilog developed. quartusii under comprehensive by
the_last_one5.13
- 使用QUARTUSII编写的cdma2000建议的发送接收系统，verilog写的-Cdma2000 proposed transmission and reception system use QUARTUSII written, verilog written
QPSK
- quartusii下使用verilog编写的qpsk映射和解映射，比较简单的学习型代码-quartusii use verilog to write qpsk mapping and demapping relatively simple learning code
频率计
- quartusii 和vhdl语言利用四位频率计设计，(Four bit frequency meter design)