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aes128-rtl
- 本程序是AES128 加密算法硬件实现源程序。符合NIST FIPS-197标准
rtl
- 基于脉动结构的有限域乘法器，verilog代码-Based on the pulse of the structure of finite field multipliers, verilog code
LIP1611CORE_AES128_SEC_UWB
- AES 128 Synthesisable RTL code
64R4SDFpoint_FFT
- 该工程实现了一个64点FFT，verilog编写，采用R4SDF结构，通过Modelsim功能仿真，压缩包里有rtl代码，dc脚本，输出报告。-The project implements a 64-point FFT, verilog compiled by R4SDF structure, through the Modelsim functional simulation, compression bag with rtl code, dc scr ipt, the output repo
RTL-to-Gates-Synthesis-using-Synopsys-Design-Comp
- RTL-to-Gates Synthesis using Synopsys Design Compiler.rar
aes_pipe_latest.tar
- AES Pipe RTL Code, Support 128/192/256bits key Come from OpenCore.-AES Pipe RTL code
rtl_wangjiangxing
- ecc椭圆算法RTL,verilog经过验证-ecc verilog
HASH
- hash加速器的verilog实现，也用于fpga或asic-hash verilog rtl
AES
- aes源码verilog带有仿真环境，可用于FPGA实现-aes verilog rtl
pka_engine
- rsa ecc加速器源码和仿真环境，用于fpga-rsa ecc rtl and sim
rtl
- 实现sha1（128）杂散算法。输入为64bit，输出160bit。(Implementation of SHA1 (128) algorithm. The input is 64bit, and the output is 160bit.)