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uartok
- 采用verilog编写的串口通信程序，采用了状态机设计！程序简单，消耗资源少-Serial communication written by verilog hdl. It is designed with FSM. The program is simple,and consume resource is few.
verilog_UART
- UART verilog hdl 实现-UART Verilog HDL achieve
uart16550
- uart16550 ＩＰ核 ＨＤＬ源代码，对设计自己uart的人员和学习串口通讯有一定的参考价值！其中，附有详细的所明文档！-uart16550 IP HDL source code, uart to design their own study of serial communication and has some reference value. Which, with detailed documentation as prescribed!
uart2iic
- UART转I2C的Verilog HDL代码，由北京邮电大学《VerilogHDL设计与EDA技术基础》教师编写
demo_24c01a
- 24C01A的Verilog HDL仿真代码，用于I2C接口模块的测试，由北京邮电大学《VerilogHDL设计与EDA技术基础》教师编写
rec
- uart串口通信程序 用VERILOG HDL 编写 可以有效应用于FPGA上
通过 SPI 接口控制 I2C总线上音频器件数据流
- 用cycloneII的C020芯片来控制SPI转I2C的Verilog HDL程序
usb20_ipcore_usb_funct
- usb的芯片ip core. 用HDL描述，适合asic/fpga人员参考或使用。USB ip core for ASIC/FPGA designers.-usb chips ip core. with HDL descr iption suitable for asic/fpga staff reference or use. USB ip core for ASIC/FPGA designers.
ldpc
- 最近在做毕设，ldpc码的编解码实现，这个是verilog实现。-Recently completed the set up to do, ldpc code codec implementation, this is the Verilog implementation.
UART_receiver
- 通用串口收发器的移位寄存器 是verilog hDl编写-uart_reg
SerialPort
- 一个用verilog HDL 编写的串口发送程序，可以下载到FPGA中。已经在ActelFPGA中试过了，很好用。稍微修改之后，可以与Xilinx和Altera公司的FPGA兼容。-A programe dialogue to transmit a serial data which is writen by Verilog HDL.
verilogHDL
- RS（31，15）译码关键步骤的veilog HDL算法实现，包括关键方程求解，错误位置估计，错误值计算等-RS (31,15) decoding a key step in the algorithm veilog HDL, including key equations, position estimation error, error value, such as
cordic.tar
- 用Verilog HDL写的CORDIC算法程序，用于极坐标的笛卡尔坐标的呼唤。采用了宏定义，可以方便的配置CORDIC的参数，值得学习。此程序来自OPENCORES，我用过，很好。-A verlog HDL programme which implement CORDIC algorithem for Polar to Rectangle transform.
Serial
- 串口通讯程序，用的芯片是 CP2102， Verilog HDL 程序，编译通过，完全可用-Serial communications program, using chip CP2102, Verilog HDL program, compiled by completely available
hdlcodermimo
- hdl coder mimo hdl coder mimo hdl coder mimo-hdl coder mimo hdl coder mimo hdl coder mimo hdl coder mimo
hdlcoderviterbi
- hdl coder viterbi hdl coder viterbi hdl coder viterbi-hdl coder viterbi hdl coder viterbi hdl coder viterbi hdl coder viterbi
code
- <基于Verilog HDL的通信系统设计>源码，包含ASK,FSK,PSK,QPSK,PPM等的调制解调-< Verilog HDL-based communication system design> source, including ASK, FSK, PSK, QPSK, PPM and other modem
lab4
- verilog代码例程，主要用于hdl语言初学者对于verilog的学习(verilog example Code routines, it is mainly used for the verilog HDL language beginners to learn)