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verilogHDL
- RS(31,15)译码关键步骤的veilog HDL算法实现,包括关键方程求解,错误位置估计,错误值计算等-RS (31,15) decoding a key step in the algorithm veilog HDL, including key equations, position estimation error, error value, such as
XOR_tree
- This source code is a check node unit for LDPC decoder. The language is Verilog HDL.