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uart16550
- uart16550 ＩＰ核 ＨＤＬ源代码，对设计自己uart的人员和学习串口通讯有一定的参考价值！其中，附有详细的所明文档！-uart16550 IP HDL source code, uart to design their own study of serial communication and has some reference value. Which, with detailed documentation as prescribed!
uart16550
- uart source code from opencore
uart16550
- uart16550 is a 16550 compatible (mostly) UART core. The bus interface is WISHBONE SoC bus Rev. B. Features all the standard options of the 16550 UART: FIFO based operation, interrupt requests and other. The datasheet can b
mini_or1200
- openrisc mini_or1200, 包括 or1200、uart16550、dbg_interface、mem_if(片上内存)这几部分。-openrisc mini_or1200, including or1200, uart16550, dbg_interface, mem_if (memory chip) in these parts.
uart16550
- Ｕａｒｔ 串口的verilog实现已调试通过-verilog
UART16550
- UART控制器，集成FIFO，寄存器，数据位宽8位-UART controller, with FIFO, register, databus 8bits
uart16550_latest.tar
- UART16550是较为通用的串口协议，压缩包内有4个文件可供选择，直接提供RTL源码，可直接导入到工程内。-Uart16550 core is used for Serial Commuication.There are 4 folders in the zip package and have the verilog RTL which can be added in the project.