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jiafa
- vhdl的加法计算，用于初学者熟悉vhdl语言-for the newers to get familier with vhdl
jiafa
- 可以进行简单的时钟模拟，运用了中断和定时器进行定时。-Can be a simple analog clock using a timer interrupt and the timer for.
jiafa
- FIR源码ccs2.2版本编译通过，不过不能在3.3版本下正确运行-FIR source ccs2.2 version compiles, but can not run properly under version 3.3
jiafa
- 基于QUTER的VHDL言语的加法器设计-Based on the words of the QUTER VHDL adder design
jiafa
- 实现AD采样进来的5路信号相加、比较，判决，输出控制码 实现数字自动增益控制-AD sample the incoming signal sum, comparison, judgment, and output control codes to implement digital AGC