搜索资源列表
标准SDR SDRAM控制器参考设计_verilog_lattice
- 标准SDR SDRAM控制器参考设计，Lattice提供的verilog源代码-standard SDR SDRAM controller reference design, the Lattice Verilog source code
9.8_DISP256_GUO
- 基于Verilog-HDL的硬件电路的实现 9.8 基于256点阵的汉字显示 9.8.1 单个静止汉字显示的设计原理及其仿真实现 9.8.2 单个静止汉字显示的硬件实现 9.8.3 多个静止汉字显示的设计原理及其硬件实现 9.8.4 单个运动汉字显示的设计原理及其硬件实现 9.8.5 多个运动汉字显示的设计原理及其硬件实现 -based on Verilog-HDL hardware Circuit of 9.8 based on t
uart_core_vhdlORverilog
- 串uart的vhdl，verilog，lattic实现原码 里面有四个文件,分别UART 源码 (lattice version)\\uart 源码 (Verilog)\\uart 源码 (VHDL)\\uart16550.tar-uart series of vhdl and verilog. lattic achieve the original code, there are four documents, Source respectively UART (lattice versi
Lattice_Verilog
- 本文讨论了AR模型及线性预测的原理，在浮点型DSP TMS320C6713B上实现了语音信号线性预测系数(LPC)的提取，并利用LPC系数用Verilog语言实现了AR模型的Lattice结构。
Verilog[lattice]
- 这是一有很好价值的verilog教程,本人就因此获意非浅,再次贡献给大家,希望大家有所帮助.
并口的CPLD烧录线，通过跳线支持三大厂家的CPLD/FPGA(Altera,Xilinx,Lattice)
- 并口的CPLD烧录线，通过跳线支持三大厂家(Altera,Xilinx,Lattice)的CPLD/FPGA烧录,附有电路图与Verilog HDL文档.使用的芯片为XC9572XL-VQ64
UART_VHDL_Verilog_Lattice
- 本压缩包中含有串口程序的VHDL,Verilog，Lattice三种版本的代码，均已实现。在压缩包中，含有非常详细的串口的实现规格。各种版本的代码中，含有完成的源文件，测试文件，模拟文件。-This compressed package contains serial process VHDL, Verilog, Lattice three versions of the code, have been achieved. In the compressed package, contains
LatticeMico8_v3_0_Verilog
- The LatticeMico8™ is an 8-bit microcontroller optimized for Field Programmable Gate Arrays (FPGAs) and Crossover Programmable Logic Device architectures from Lattice. Combining a full 18-bit wide instruction set with 16 or 32 General Purpose r
uart16450
- uart 16450合集,xilin altera lattice-collection of uart controller 16450
I2C_xo
- IIC的verilog源码，可以在Lattice的XO DEMO板上运行的IIC代码。内附说明文件-IIC' s verilog source code, you can Lattice' s XO DEMO board to run IIC code. Included documentation
ddr_sdr_latest.tar
- 一款DDR400的驱动程序，使用VERILOG语言，在LATTICE—ECP2m的FPGA芯片中实际测试。-A DDR400 driver, using VERILOG language, LATTICE-ECP2m actual test of the FPGA chip.
LED_FINAL2
- 用Verilog HDL 实现16*32LED点阵的静态显示-Using Verilog HDL to achieve 16* 32LED lattice static display
FPGA_UART
- 用Verilog语言实现的FPGA UART独立收发模块 思路简单，代码简洁。在Lattice LFE3EA VERSA开发板上验证通过,编译器Lattice Diamond. 功能：串口收到数据后立即回传，此后每一秒串口数据+1再发送。-Using Verilog language independent of FPGA UART transceiver idea is simple, concise code. Development board in Lattice LFE3EA
ddr2_demo
- lattice 操作DDR2控制器verilog源代码-the verilog source code of ddr2 control of lattice
Verilog_lattice-fpga
- Verilog教程lattice FPGA-Verilog tutorial Lattice FPGA
ddr_top
- This VHDL or Verilog source code is intended as a design reference // which illustrates how these types of functions can be implemented. // It is the user s responsibility to verify their design for // consistency and functionality through the
ddr_sig
- This VHDL or Verilog source code is intended as a design reference // which illustrates how these types of functions can be implemented. // It is the user s responsibility to verify their design for // consistency and functionality through the
ddr_data
- This VHDL or Verilog source code is intended as a design reference // which illustrates how these types of functions can be implemented. // It is the user s responsibility to verify their design for // consistency and functionality through the
lattice_ddr_verilog-for-orca4
- 莱迪思的DDR控制器源码（包括仿真与说明文档），DDR为MT46V16M8，Verilog-The DDR controller source of Lattice (including simulation and documentation), DDR is MT46V16M8, Verilog
本小姐的介绍
- 俄罗斯方块V2.0 游戏用四个方向键控制： 左右键分别左移一格，右移一格； 好啊(The Tetris V2.0 game is controlled by four direction keys: the left and right keys move left one, and the right shift is a lattice.)