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float_mul_verilog
- 浮点乘法verilog代码，浮点格式遵循 IEEE754 标准。-Float Point Multiply , im verilog
multiply
- Verilog hdl语言 常用乘法器设计，可使用modelsim进行仿真-Verilog hdl language commonly used multiplier design, can use the ModelSim simulation
multiply
- 由verilog编写的乘法器，通过两个文件的调用实现。由于子模块的调用使得程序简化了许多。-Prepared by the Verilog multiplier, through the realization of the two documents call. As the sub-modules to simplify the procedure call makes a lot.
fir_parall
- 基于verilog的fir滤波器设计，用的并行结构。在前面基础上加入四级流水（加法器，并行乘法器，乘法结果相加两级），通过验证。-Verilog-based design of fir filter using the parallel architecture. In front of the basis of adding four water (adder, parallel multiplier, multiply the result of the sum of two), throu
multilyUnit1
- a verilog programmed multiply unit algorithm
multiplyUnit2
- verilog multiply algorithm
presentar
- Verilog code calculator, add, rest, multiply, and increment-Verilog code calculator, add, rest, multiply, and increment
multiply
- 简单的乘法器，用Verilog实现 multiply-multiply
CourseDesign
- 用Verilog实现一位原码浮点数乘法器，按照累加的方式，逐位相乘，再相加。-Verilog realization of an original code with floating point multiplier, in accordance with the cumulative way, bit by bit multiply, then add.
verilog_calculator
- 用verilog编写的简易计算器代码。通过一位全加器组成电路，可以实现加法、减法和乘法，并在七段数码管上显示出十进制的结果。-Simple calculator with code written in verilog. Composed by a full adder circuit, can add, subtract and multiply, and in the seven-segment LED display on the decimal result.
multi_cycle_Verilog
- this code has written in verilog and it is about multi cycle mips processor .This code can do alot of jobs for examole,add ,addi ,addiu,and ,andi,ori ,mfhi.mfho,xor,slt,slti,ssw,lw,lui ,jal ,mult ,multu,... and it can multiply two input inter less th
floating_point_multiplier_verilog
- This code has written in verilog and it can multiply two floating point number with IEEE 754 standards and the out put of this code is in IEEE 754 standard.We have to put input in binary and the out put is also in binary.
Multiplier16
- 本文设计了一种可以实现16位有符号/无符号二进制数乘法的乘法器。该乘法器采用了补码一位乘（Booth算法), 简化了部分积的数目, 减少了某些加法运算,从而提高了运算速度。该乘法器利用Verilog代码实现，通过Modelsim软件对相应的波形进行仿真验证，并通过QuartusII软件对源码进行编译综合。-This paper designed a 16 signed/unsigned binary number multiplication of the multiplier can be a
MAC
- 在FPGA硬件上，使用verilog语言编写的一个乘累加器程序。-FPGA hardware, a multiply accumulator verilog language program.
multiplying-unit
- fpga verilog入门经典系列完整版，下载即用:乘法器-fpga verilog multiply
4bitmultiplier
- its a verilog coding of a multiplier. it multiply 2 values each of width having 4bit
lab3
- booth算法移位乘 使用verilog(Booth algorithm shift multiply Verilog)
计算器
- 用verilog语言实现了一个计算器alu，实现加减乘除的简单计算。(Using Verilog language to achieve a simple calculator ALU, computing add, subtract, multiply and divide.)
spi_8r8w
- 同时实现多个SPI从设备的连续读写，读写字节数可变化(implement multiply spi slave read/write operation, and the operation's bytes can be changed)