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脉冲记时CPLD
- 工作原理： 脉冲输入，记录30个脉冲的间隔时间（总时间），LED显示出来，牵涉到数码管的轮流点亮，以及LED的码。输入端口一定要用个 74LS14整一下，图上没有。数码管使用共阴数码管。MAXPLUS编译。 测试时将光电门的信号端一块连接到J2口的第三管脚，同时第一管脚为地，应该与光电门的地连接（共地）。 开始测试： 按下按键，应该可以见到LED被点亮，指示可以开始转动转动惯量盘，等遮光片遮挡30次光电门后， LED熄灭，数码管有数字显示，此为时间值，单位为秒，与智
gongchengsheji-477
- 基于logmap算法的vhdl的实现。 通信系统的log—map算法数字vhdl的实现-logmap algorithm based on the achievement of VHDL. The communication system log-map algorithm to achieve the number of VHDL
110detector_lab
- 一个简单的探测110三位的探测器，用逻辑图和vhdl描述，包括实验报告和测试图。-a simple survey of 110 three detectors, and a logical map vhdl descr iption, including reports and experimental test plan.
s_machine
- right.vhd 序列发生器 s_machine.vhd 序列检测器 波形图.doc 程序运行波形-right.vhd s_machine.vhd sequence generator waveform sequence detector map. doc procedures Waveform
9.7_DIRIVER_control
- 基于Verilog-HDL的硬件电路的实现 9.7 步进电机的控制 9.7.1 步进电机驱动的逻辑符号 9.7.2 步进电机驱动的时序图 9.7.3 步进电机驱动的逻辑框图 9.7.4 计数模块的设计与实现 9.7.5 译码模块的设计与实现 9.7.6 步进电机驱动的Verilog-HDL描述 9.7.7 编译指令-\"宏替换`define\"的使用方法 9.7.8 编译指令-\"时间尺度`timescale
jiaotongdengcodes
- 实例制作的一个有关交通灯的VHDL代码，从各模块到顶层文件的代码一一列出，详细周到，附带仿真波形图和芯片管脚锁定的相关内容，绝对物超所值。-produced an example of the traffic light VHDL code, from the module to the top of the document sets out a code on January 1, thoughtful details, fringe simulation waveform map and
DDS小数分频
- 文件列表(点击判断是否您需要的文件，如果是垃圾请在下面评价投诉): DDS小数分频 ...........\Block1.vhd.bak ...........\db ...........\..\add_sub_9mh.tdf ...........\..\DDS.asm.qmsg ...........\..\DDS.asm_labs.ddb ...........\..\DDS.cbx.xml ...........\..\DDS.cmp.
aes
- aes的加密解密算法的源代码以及测试源代码和仿真结果图-aes encryption decryption algorithm source code and test source code and simulation results map
wavegenerator
- 开发环境为QuartusII，能产生正弦波、三角波、方波和锯齿波，幅度为5V，采样为8位，在开发板已经验证通过，有详细的波形图和管脚分配图。-Development environment for QuartusII, can generate sine wave, triangle wave, square wave and sawtooth wave, ranging from 5V, sampling for 8, in the development board has to verif
mux21a
- 2选1多路选择器的VHDL完整描述，即可以直接综合出实现相应功能的逻辑电路及其功能器件。图6-1是此描述对应的逻辑图或者器件图-2 election more than one MUX complete descr iption of the VHDL, which can be directly integrated to achieve the corresponding function logic devices and their functions. Figure 6-1 is th
bb
- CPLD可编程逻辑芯片上实现信号发生器的方法和步骤，系统采用自顶向下的设计方法，以硬件描述语言VHDL和原理图为设计输入，利用模块化单元构建系统。-CPLD programmable logic chip Signal Generator methods and steps system uses top-down design approach to hardware descr iption language VHDL and principles of map design input,
FPGA
- 将立体杂波图应用于气象杂波的CFAR处理，根据当前杂波环境的变化实时地产生杂内杂外标志，从而选择不同的信号处理支路处理当前气象杂波，提高了雷达的检测性能，降低了虚警概率。-Will be applied to three-dimensional meteorological clutter Clutter Map CFAR of treatment, according to the current clutter environment generated in real time with
LEDVHDL
- LED控制VHDL程序与仿真，有源程序和仿真图，希望对大家有用-VHDL program LED control and simulation, there is source code and simulation map, useful for all of us hope
FPGA_NEW_APPROACH_TO_IMPLEMENT_CHAOTIC_GENERATOR.
- In this paper, a new method is introduced to implement chaotic generators based on the Henon map and Lorenz chaotic generators given by the state equations using the Field Programmable Gate Array (FPGA). The aim of this method is to increase the freq
Pseudo-Random_Bit_Sequence_Generator_by_FPGA
- A spatiotemporal chaotic map is digitized to develop a highly paralleled PRBS generator that accommodates to FPGA (Field Programmable Gate Array) implementation in present paper.
singt
- 用VHDL语言描述的用锁存器，加法计数器，ROM存储器构成的RTL图-VHDL language used to describe the use of latches, adding counters, ROM memory map consisting of RTL
song
- 歌曲是什么名字我忘了，代码仅提供一个用verilog编写音乐的模板，想编写什么音乐就往里边套用格式就行了。 本程序无法用软件实现仿真音乐效果，当然可以仿真波形输出，真实音乐效果需用开发板仿真才行，所以就不附仿真图了 用quartus2软件打开即可。 -What are the names of songs I forgot, the code with verilog only prepared to provide a template for the music, what mu
eda
- cpld开发板电路图，刚下载的，还不错，给大家看看。-the map of cpld developed board。
MAPdecodingexample
- MAP decoding is a simple method to decode turbo codes
map
- map verilog for xilinx