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2011年电子设计大赛e题《简易数字信号传输分析仪》
- 2011年电子设计大赛e题《简易数字信号传输分析仪》verilog源代码，实现后端采样同步时钟-E Electronic Design Contest 2011 problem " simple digital signal transmission analyzer" verilog source code sample to achieve the back-end clock synchronization
b_pro3_restored
- 2011年电子设计大赛e题《简易数字信号传输分析仪》verilog源代码，分信号源和分析仪两部分-2011 electronic design competition e question the simple digital signal transfers analyzer "verilog the source code, and the points the signal source and the two parts analyzer
debounce_2_Verilog
- 用VerilogHDL编写的按键消抖程序 分频产生100Hz的按键采样时钟,采样时钟周期为10ms, 按键按下后,产生时间为10ms的低电平信号,即LED亮10m-*Project Name :debounce *Module Name :debounce *Target Device :Any Altera FPGA/CPLD Device *Clkin : 50MHz *Desisgner : zhaibin *Date : 2011-11-
2011-03-09
- 基于quartus II cycloneII verilog分频器-Divider based on quartus II cycloneII verilog
UART
- This vhdl code has a simple implementation of an UART receiver. This code was generated march 2011 as a universuty project
2011-EDA-1
- 2011全国电子创新设计竞赛培训资料，第一手原创资料-EDA-Electronic Innovate Design
project-report-2011
- DIGITAL TEMPERATURE MONITORING DEVICE USING FPGA- BY SOMVANSHI-DIGITAL TEMPERATURE MONITORING DEVICE USING FPGA- BY SOMVANSHI
EDK13.1
- xilinx 2011全国电子设计大赛赞助商 EDK 应用设计讲述了其嵌入式的应用-xilinx 2011 National Electronic Design Competition Sponsored EDK embedded application design describes its application
angel_php
- Describe: VHDL Cookbook including many useful building blocks. Develop tools: VHDL | File size:4374KB | Downloads: 0 [TCP/IP Stack] back4.zip <ding_xinyi> upload at 2011-9-17 4:40:30 Describe: UDP java reference reliable transmission,
digital_sigal_generator
- 全国大学生电子设计大赛源代码，Verilog HDL ，2011年最后一题，即E题代码-National Undergraduate Electronic Design Contest source code, Verilog HDL, 2011 the last one question, that question the code E
2011_Intersil
- 介绍了intersil在监控领域的芯片产品和典型应用-Introduced intersil chips in surveillance products and typical applications
debounce_1_Sch
- 用QuartusII原理图形式编写的按键消抖程序,分频产生100Hz的按键采样时钟,采样时钟周期为10ms, 按键按下的时间与产生低电平信号的时间相等,按键按下的时间与LED灯亮的时间相等-*Project Name :debounce_Sch *Module Name :debounce_Sch *Target Device :Any Altera FPGA/CPLD Device *Clkin : 50MHz *Desisgner : zhaibin *D
ppt4aix4sopc
- 基于AXI4的sopc开发讲义,2011年电子大赛的辅导材料-powerpoint for aix4 sopc development
e_pro_restored
- 2011年电子设计大赛e题《简易数字信号传输分析仪》verilog源代码，分信号源和分析仪两部分-2011 electronic design competition e question the simple digital signal transfers analyzer "verilog the source code, and the points the signal source and the two parts analyzer
2011-diansai-E
- 2011年 电赛 E题 简易数字信号传输性能分析仪FPGA信号发生部分 包括m序列，伪随机序列，曼彻斯特编码 程序 和单片机部分程序-2011 CEC E title simple digital signal transmission performance analyzer FPGA signal part of the program and single-chip part of the program
grlib-gpl-1.1.0-b4108
- gaisler公司在2011年发布的的leon3的源代码！-source code of leon3
ex
- 自己写的一个程序 verilog 电子设计大赛20-Himself wrote a program Verilog Electronic Design Contest 2011
2011-04-27-Stepper-motor-control-TI-DRV8332DKD.zi
- Stepper-Motor Control for TI-DRV8332DKD. Operation with steps of N kHz, while n > 1. Functionality: Forward, backward, hold, stand-by
1
- LCD控制VHDL程序与仿真2011.8修改，实现方便-LCD control procedures and VHDL simulation 2004.8 modify and easy to achieve
s5pv-u-boot-LCD-display
- s5pv-u-boot-2011.06之增加LCD显示功能-s5pv-u-boot-2011.06 Increase LCD display function