搜索资源列表
two_d_dct_serial
- altera公司提供的适用于包涵DSP内核的FPGA的二维DCT变换源码，语言是：verilog 性能不错，不过资源消耗有点大，可以用来学习多项式变换的DCT算法-ALTERA companies covered in the application of FPGA DSP core 2D DCT source language is : Verilog performance is good, but a bit large consumption of resources can be us
two_d_dct_serial
- Verilog codes for 2D Discrete Cosine Transform (DCT)
2DImageFilterByVHDL
- 用VHDL语言编程实现2维图像的滤波算法，简单精辟-VHDL programming language used to achieve 2-D image filtering algorithm, simple brilliant
dct2
- 这个是一个基于FPGA的数字图像的整数DCT变换程序，程序高性能地实现了2维DCT变换。-This is an FPGA-based digital image of the integer DCT transform process and procedures to achieve high-performance 2-D DCT transform.
projekt
- Dct 2d in vhdl + descr iption -Dct 2d in vhdl+ descr iption
xapp610
- Verilog code for 2D-DCT with detailed documentation.
Imagem2DGraphics
- Imagem 2D Graphics display-Imagem 2D Graphics display
ch3_dct
- fpga dct变换，用以视频压缩和处理图像-fpga dct
Frame_2D
- 自己编写的通用2维框架结构，可以计算模态、静力、动力响应-A 2D frame building of ANSYS developed by myself, can calculate modal, static and dynamic response
dct
- all ok...4 Dec 2009 ... In this method the 2-Dimensional DCT is obtained by taking two ... column-wise 1D DCT is ascertained which gives the 2D DCT of the data. ... The design is done in Verilog HDL and the simulation is done in Modelsim 6.3b.
dct
- JPEG Compression and Ethernet Communication on an FPGA
dwt2d
- discrete wavelet transform - 2d
testDWT2D
- 2d discrete wavelet transform.
Convolution_filter-fpga
- Implementation of a 2D Convolution Filter on FPGA. Performance evaluation between CPU, GBU and FPGA
VLSI-Architectures-for-Discrete-Wavelet-Transform
- VLSI architecture and VHDL codes for 1D and 2D DWT and IDWT schemes.
top_interface
- top integrated block for 2d graphics engine
dct
- 基于FPGA的图像压缩算法程序，自己写的，可以参考一下-FPGA-based image compression algorithm, write your own, you can refer to
graph-acceleration-verilog
- 2D图形加速，里面有串口模块。可以综合，为本人毕业设计。-2D graphics acceleration, which has the serial port module. Can be integrated, as my graduation project.
DCT8_final
- 二维dct算法的fpga实现及验证，采用VHDL语言编写。-2D-dctThe FPGA realizing algorithm
2D-FILTER
- VERILOG CODE FOR 2D FIR FILTER