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ds18b20
- 单路DS18B20的verilog HDL 代码，精度为1℃无须转换数据，直接输出结果。占用300个LE资源。-Single DS18B20 the verilog HDL code, and an accuracy of 1 ℃ without converting the data, direct output. Occupy 300 LE resources.
pump-program
- s7-300泵轮换程序,需要用西门子step7打开-s7-300pump program，It must be open by step7 software
All_Digital_DC2DC_Converters_on_FPGA
- The FPGA can realize a more optimized Digital controller in DC/DC Converters when compare to DSPs. In this paper, based on the FPGA platform, The theoretical analysis, characteristics, simulation and design consideration are given. The methods to imp
project_spartan2
- this is a spartan 2 project
verilog_300examples
- verilog的300个例子，很全的，我自己都试过-verilog 300 examples, it is full, and I have tried
verilog_300examples
- 该文件集结了verilog的300个经典实例，为初学者提供了良好的工具-The document brings together 300 classic example verilog for a good tool for beginners
m_serial
- m序列产生。3个300阶m序列级联，产生近似随机的数数。输出包括串行输出的随机时钟和并行输出的32位的随机数。-m sequence generation. 3 300 m-order sequence cascade, resulting in an approximate number of random numbers. Output 32 of the random numbers and the parallel clock output comprises serial output
设计IIR滤波器
- 设计IIR滤波器（带通，三种方法，fs=2000HZ,通带频率300~500HZ，阶数自选，画频率特性并分析比较）.
code
- 某数据传输系统，试图利用300-3400Hz的话音通 道进行载波传输，波形信道为加性高斯白噪声信道。 –采用线性传输，收发两端拟采用滚降系数0.5的根 号升余弦滤波，以解决采样点失真问题。 –以下仿真采用无记忆采样信道模型，其中受器件限 制，复基带采样点平均功率受限为1，复基带采样 点噪声功率为可调参量-A data transmission system, trying to use 300-3400Hz voice channel for carrier transmission, wave
AD9883 iic_v1.0_for_sim
- 程序用于配置AD9883芯片寄存器，采用iic协议。 FEATURES Industrial Temperature Range Operation 140 MSPS Maximum Conversion Rate 300 MHz Analog Bandwidth 0.5 V to 1.0 V Analog Input Range 500 ps p-p PLL Clock Jitter at 110 MSPS 3.3 V Power Supply Full Sync Proces