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scaler
- VHDL描述的简易图像缩小模块，将PAL制720×576的图片缩小为512×410，采用最近临域法，13.5MHz时钟下可实时处理PAL视频。
512点FFTVerilog实现
- 关于FFT Verilog代码实现的源代码
sin_cos_rom
- 9bit、512个数据点（1/4周期）的正弦余弦ROM查值表-9bit, 512 data points (1/4 cycle) check the value of the sine and cosine table ROM
IFFT-RTL
- 本人自己写的可实现512点或64点IFFT算法的verilog硬件代码-the verilog code for IFFT algorithm
S29gl128p_VHDL
- The Spansion S29GL01G/512/256/128P VHDL-The Spansion S29GL01G/512/256/128P VHDL
code
- SHA_1算法填充部分的VHDL实现，让输入的数据可以转换为SHA_1算法所需要的512bit的数据-SHA_1 algorithm filling part of the VHDL realization, let the input data can be converted to SHA_1 algorithm need 512 bit data
FIFO
- 512×8bid的FIFO 含工程文件，基于QUARTUs-512 × 8bid the FIFO with the project document, based on the QUARTUsII
Flashcontrollerxilinx
- Single power supply operation — Full voltage range: 2.7 to 3.6 volt read, erase, and program operations — Separate VCCQ for 5 volt I/O tolerance n Automated Program and Erase — Page program: 512 + 16 bytes — Block erase: 8 K + 256 bytes
RAM
- 曾经做过一电子竞赛课题部分，硬件描述语言VHDL做数据存储器512位存储深度，-Competition has been a subject of electronic parts, hardware descr iption language VHDL do data memory storage depth of 512,
512
- several examples in Sram access in Spatan 3E
fir_512_378_mux
- 512阶高速FIR成型滤波器，四相位复用，树形加法和多级流水线结构。-512-order high-speed FIR shaping filter, four-phase re-use, tree addition and multi-stage pipeline structure.
armledctl
- EPM240+IS61LV1024+VERILOG实现LED显示控制,1红+1绿,1280*512,与AT91SAM7S64接口-EPM240+ IS61LV1024+ VERILOG to achieve LED display control, 1 red+ 1 green, and 1280* 512, and AT91SAM7S64 Interface
fft2
- 512点8位基2fft程序。基于 vhdl/verilog。已仿真布线通过。-512 points, eight base 2fft program. Based on vhdl/verilog. Simulation layout has been adopted.
freq_divider
- 8bit分频器，最高256*2=512 分频，使用emacs编写源文件，iverilog仿真通过-8bit divider, the maximum 256* 2 = 512 min frequency, use emacs to prepare source file, iverilog simulation success
fft
- 不定点的fft算法，当前可选择64,128,256,512,1024个点数，可自行添加其他-The fft algorithm is not fixed, the current choice 64,128,256,512,1024 one point, they are free to add other
Sinusoidal
- sine generator in rom with 512 points.
2DPSK-linan
- 全数字2DPSK调制解调系统，为VHDL语言。包括512分频器，M序列发生器等。整个过程完成2DPSK的调制与解调。-The full the digital 2DPSK modem system for the VHDL language. Including the 512 divider, the M-sequence generator. The whole process is completed 2DPSK modulation and demodulation.
rsa_512_latest.tar
- 512位RSA VHDL 算法,使用了蒙哥马利模乘算法，该程序写的有些麻烦，但是对于初学者学习是够了。-512 bit RSA VHDL algorithm,it is open cores.it is very good for beginers to study.
512_RSA
- 512位RSA VHDL 算法,使用了蒙哥马利模乘算法，该程序写的有些麻烦，但是对于初学者学习是够了。-512 bit RSA VHDL algorithm,it is open cores.it is very good for beginers to study.
FFTSim.m
- 仿真FFT参数对采用FFT算法分析信号频谱的影响。产生频率分别为2Hz，2.05Hz的正弦波合成信号，采样 频率＝10Hz。根据（8-8）式，要实现分辨两个单频信号的目的，DFT的序列长度必须满足 。分别仿真3种 情况下的FFT变换：１）取 的128点数据，计算FFT；２）将128点 以补零的方式加长到512点，计算FFT； 3）取512点 ，计算FFT-fft simulation matlab