modelsim-win32-6.5-se 解破文件。 功能全。可以用到2020年。可以用于VHDL,VERILOG, system C 等模拟及混合模拟。-modelsim-win32-6.5-se solutions broken files. full loaded. expired in 2020.. Can be used for VHDL, VERILOG, system C simulation and mixed simulation.

SRIO接口物理层的实现代码，非常复杂，完全自己用verilog编写，支持5G速率，可以作为开发参考-SRIO interface implementation code, the physical is very complex, completely written in verilog, support rate of 5 g, will be helpful to the development

PCIE控制器，FPGA实现PCIE通讯，速率高达5Gbps每个通道。-PCIT Controller ，Which speed up to 5G per lane