搜索资源列表
cpldcontrol
- 一段cpld的控制程序，可以进行传并转换，读写接口，每秒64k-a cpld control procedures can be done - and switching to read and write interface per second 64k
gen_nx64k
- N×64K数控分频模块，可将2.048M时钟分频为一个NX64k的时钟，在E1复用设备上应用。 -N × 64K NC frequency module can be 2.048M NX64k clock frequency for a clock, the E1 multiplexing equipment apply.
SDH
- SDH开销的接收处理，要求： 1， A1和A2字节为帧头指示字节，A1为“11110110”，A2为“00101000”，连续3个A1字节后跟连续3个A2字节表示SDH一帧的开始。要求自行设计状态机，从连续传输的SDH字节流中找出帧头。 2， E2字节为勤务话通道开销，用于公务联络语音通道，其比特串行速率为64KHz(8*8K=64)。要求从SDH字节流中，提取E2字节，并按照64K速率分别串行输出E2码流及时钟，其中64K时钟要求基本均匀。（输出端口包括串行数据和64K串行时钟）
tdm_latest[1]
- TDM，就是时分复用。本程序完成4通道，没通道最多32路64K信号的交换，就是说可以完成32x4个电话信号交换-TDM, is time-division multiplexing. The process is complete 4-channel, no channel up to 64K 32 to exchange signals, that can be done 32x4 telephone signal exchange
HDB3_coder
- 实现了将64K低速NRZ码复接成2.048M高速HDB3码及其解复接过程，同时还用同步状态机剔除假同步和假失步的状态 -Achieved the 64K low-speed NRZ code 2.048M into high-speed multiplexing and demultiplexing HDB3 code then the process also removed using false synchronous state machine synchronization and f
vhd_SDH
- 实现从连续传输的SDH字节流中找出帧头、提取F1字节，并按照64K速率分别串行输出F1码流及时钟，其中64K时钟要求基本均匀。文件包含报告文档-SDH transmission from a continuous stream of bytes to identify header, extract F1 bytes, respectively, in accordance with 64K-rate serial output bit stream and clock F1, of which
projiect
- 简单数字系统的系统级设计，完成E1clk 时钟1/32 分频产生64K 时钟的设计-A simple system-level design of digital systems to complete E1clk clock 1/32 min 64K clock frequency generated design
SDHdet
- 从SDH字节流中，提取E2字节，并按照64K速率分别串行输出E2码流及时钟，其中64K时钟要求基本均匀。-SDH byte stream from the extracted E2 bytes, and the serial output in accordance with rates of E2 64K stream and clock, which clock 64K basic uniform requirements.
testHDLADJ64M
- 64k 帧头的猫述与实现，以及帧的误判以及相关的处理办法-64k header cat references and implementation, as well as false positives and the associated frame approach
zhongji
- 基于vhdl的dds信号发生器程序，具有一致十k调频功能，输出32k及64k正弦波-Based on the dds signal generator vhdl program has a consistent ten k FM function, 32k and 64k sine wave output
DW8051
- verilog代码，51内核，是DW8051，8K ram 64K rom强大版本-verilog code, 51 cores, is DW8051, 8K ram 64K rom powerful version