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CH7CH4CH2CH1VHDL 数字电路参考书所有程序7
- CH4CH2CH1VHDL 数字电路参考书所有程序7-CH4CH2CH1VHDL digital circuit reference all proceedings 7
4位7段led程序
- 4位7段led源代码
4位7段led灯控制
- 4位7段led灯的控制，0000-9999动态显示
Free ARM-7 Core (Verilog) 可跑 uClinux
- 一个 Free 的 ARM-7 Core,是使用 Verilog 编成,综合后占用资源小,可以执行 uClinux 等程序或系统,内附详细说明的 PDF 档及源码 Verilog 编程等.
ispLEVER是LATTICE的CPLD、FPGA继承开发环境
- ispLEVER是LATTICE的CPLD、FPGA继承开发环境，ISPLEVER许可文件--ISPLEVER6.0-7.1的注册机,ispLEVER is LATTICE of CPLD, FPGA development environment succession, ISPLEVER license file- ISPLEVER6 .0-7.1 the Zhuceji
Quartus_II_7.0.rar
- Quartus II 7.0工程修复*。修复不能打开的工程。有人在7.2的软件下用本方法也成功修复。 他是修复这个错误： Error: Can t open project -- you do not have permission to write to all the files or create new files in the project s database directory,Quartus II 7.0 Dafa repair works. Restoration pr
part2
- Implement a 3-digit BCD counter. Display the contents of the counter on the 7-segment displays, HEX2− 0. Derive a control signal, from the 50-MHz clock signal provided on the DE2 board, to increment the contents of the counter at one-se
dsp-builder-7.2-crack
- 5款altera的FPGA开发板原理图，详细介绍了板子的构成及功能-Altera paragraph 5 of the FPGA development board schematics, detailed information on the composition and functions of board
ARM7_verilog
- arm 7 verilog code used setup soc
usbin_v1.7
- 用于cy7c68013与fpga的从FIFO通讯.版本1.7-For the CY7C68013 and FPGA communications from the FIFO. Version 1.7
newvhdl
- 在 Quartus II 7.1平台下，用VLDL写的一个计时器的程序-a timer written in VLDL in Quartus II 7.1 platform
Crack_QII72
- 对于quartus 7.2软件进行破解的工具保-For quartus 7.2 crack tools software security
74HammingCode
- 用VHDL语言编写的可以实现（7，4）汉明码编解码的程序。-Using VHDL language can be achieved (7,4) Hamming Code Codec procedures.
7
- 王金明verilog第7章 适合初学者-Wang Jinming verilog Chapter 7 for beginners
SSC
- Implement the 7 segment diplay on spartan 3
7-segment
- VHDL Design of BCD to 7-segment decoder using PROM
rafal2
- VHDL project for FPGA SPartan 3 using IseWebpack 10.1. This is an implemetation of FSM for testing 7 segment with dot point 4 digit LED display.
Quartus2_cracker_72sp2
- Quartus 7.2工具软件的破解文件， 从中国区总代理处流出。-Quartus 7.2 software tool to break a document from the Department out of the general agent in China.
dem4bit_hienthi
- the verilog source code for being an examble to counts 4-bit number and display in 7-segment.
7 Segment Interfacing
- This source is used for control 7 segments on FPGA board. It is written by VHDL