搜索资源列表
8位数字频率计
- 数字频率计~ VHDL 实现 可以实现频率的测量和现实的功能 8位-digtal frequency tester (use vhdl) can be used to test frequency (8bit)
8位相位相加乘法器
- 8位相 加乘法器，具有高速，占用资源较少的优点-eight multiplier phase together with high-speed, taking up less resources advantages
一个8位CISC结构的精简CPU
- 一个8位CISC结构的精简CPU，2还提供了编译器-an eight streamline the structure of the CISC CPU, the two also provided compiler
8位大小比较器
- 8位大小比较器的VHDL源代码，Magnitude Comparator VHDL descr iption of a 4-bit magnitude comparator with expansion inputs-eight compared with the size of the VHDL source code, Magnitude Comparator VHDL descr iption of a 4-bit magnitude comparator inputs with e
CH8CH4CH2CH1VHDL 数字电路参考书所有程序8
- CH4CH2CH1VHDL 数字电路参考书所有程序8-CH4CH2CH1VHDL digital circuit reference all proceedings 8
8位加法器
- 8位加法器的原代码,主要内容下载看了就知道-Adder eight of the original code, read the main content downloaded know
8倍频vhdl
- 该文件可用vhdl语言实现时钟8倍频，运行环境可在maxplus2和ise的仿真软件上-the document available VHDL Language 8 clock frequency, the operating environment and ideally maxplus2 simulation software
一个8位处理器结构，源码分析
- 关于一个8位处理器的分析，和源代码，VHDL语言设计，经过测试-on an eight processors, and source code, VHDL design, the test
8-CPU
- 简单的8位CPU，内含PDF文件.可自己查看详细说明-simple eight CPU, containing PDF files. They can check details
FPGA-CPLD_DesignTool(8-9-10)
- FPGA-CPLD_DesignTool(8-9-10)源代码请需要的朋友下载-FPGA-CPLD_DesignTool (8-9-10) requested the source code to their peers in need Friends Download
8-cpu
- 8位CPU的VHDL设计,16条指令系统,以及部分测试代码,开发工具是quartusii_60_pc
3-8译码器
- vhdl的3-8译码器-instantiate the 3-8 decoder
3-8
- 本文件是利用verilog实现的3-8译码器
source7-8
- verilog hdl教程135例:verilog hdl语言类似于C语言，便于学习。本文档带有源代码，7-8章-Verilog HDL 135 cases Guide : Verilog HDL language similar to the C language, to facilitate learning. This document with the source code, 7 - 8
8位加法器
- 很简单很实用的8位加法器VHDL源代码！
8路视频光端机的VHDL源码
- 8路视频光端机的VHDL源码
VHDL语言实现3—8译码器
- 应用VHDL语言编写的3—8译码器，简单易懂
8-led-VHDL
- 8位流水灯程序设计，跑马灯效果显示，里面是VHDL程序。-8 water lamps program design, which is a VHDL program
3 8
- 用VHDL多种方法实现3-8译码器,元件例化(use VHDL realize 3-8decoder)
3-8译码器VHDL描述
- 在开发板FPGA：Spartan-3E 系列，型号：XC3S500E，封装：FGT320，速度-4；利用XIlinX编程，使用VHDL语言来描述组合逻辑器件3-8译码器(In the FPGA:Spartan-3E development board series, XC3S500E, FGT320, -4 package: speed; the use of XIlinX programming, using VHDL language to describe the combination