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mult8x8
- 一个用VerilogHDL语言编写的8X8的乘法器-a Verilog HDL language used in the preparation of the multiplier 8X8
VHDL_8X8led
- 8X8点阵的VHDL实现，使用10K20，包括顶层原理图-8X8 lattice of VHDL, use 10K20, including top-level schematic diagram
keyborad
- 一个8X8的矩阵键盘的VHDL文件,并且有长安键和短按键之分,即一共能做到128个键值,扫描用的时钟用1ms的就行了
8x8IDCT
- 8x8 iDCT verilog code 一次輸入八個點
led8x8
- 8x8点阵滚动字幕显示驱动 verilog-8x8 dot matrix display driver verilog marquee
mult_piped_8x8
- 8位乘8位的流水线乘法器，采用Verilog hdl编写-8 x 8-bit pipelined multiplier, used to prepare Verilog hdl
8fifo
- 可综合的 8x8 fifo VHDL 源代码-Can be integrated 8x8 fifo VHDL source code
VHDdisplay
- VHDL汉字滚动历程 实现一个王字在8X8点阵上滚动显示-VHDL characters rolling process
programtested7.27
- 可综合的信道估计模块，包括解OFDM，解导频，用于8x8，2048点的OFDM信号的信道估计-Channel estimation can be integrated module, including the solution OFDM, pilot solution for the 8x8, 2048 points of OFDM signals in channel estimation
8x8
- Behavioral level 8x8 RAM
PROYECTO_DIGITALES_2010A
- pong game running on xboard xilinx under a matrix led 8x8 and ps2 keyboard interface
transpose_buffer
- verilog source code for transpose buffer 8x8 matrics
8-by-8-Multiplier
- 8x8 bit multiplication verilog code
display
- 摘要本实验室的理解和实现一个简单的由内而外的光栅视频显示。由于填写此实验室,你就应该欣赏一下一个光栅视频显示工作。你的设计将显示一个50x40网格上的文字8x8标准光栅显示和接受输入改变用户控制下面显示的人物。-The objective of this lab is to understand and implement a simple character-based raster video display. As a result of completing this lab, you
8by8_DCT
- The 8x8 discrete cosine transform (DCT) is widely used in image compression algorithm because of its energy compaction for correlated image pixels.
DCT-Implementation
- The 8x8 discrete cosine transform (DCT) is an efficient, real-valued transform often used in image compression. Special, fast algorithms for the DCT have been developed to accommodate the many arithmetic operations involved in implementing the DC
Cadence-Encounter
- 8x8 mulitplier. created this file using the midelsim softwre. Tested and simulated. Great waveform, so the testbench is included also. Does anybody knkow how to make a 16x16 arrray multiplier?
Part3
- Quartus for 8x8 multiplier using lpm mult module from the library of parameterized modules in the Quartus II system.
8x8led
- 基于FPGA的8X8点阵控制，显示字符。verilog语言-FPGA 8X8点阵，verilog
fifo8x8
- fifo 8x8 vhdl fifo_array is array(7 downto 0) of std_logic_vector with flag --Full fifo-- --half fifo-- --empty fifo-fifo 8x8 vhdl fifo_array is array(7 downto 0) of std_logic_vector with flag --Full fifo-- --half fifo-- --empty