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run_length_coding
- 用verilog 编写 应用于图像压缩编码中 使用行程长度编码(run lengthencoding,RLE)对交流系数(Aa)进行编码。-using Verilog prepared for image compression coding using length encoding (run leng thencoding, RLE) on the exchange coefficient (Aa) coding.
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- xilinx环境下开发vhdl语言串行接口设计-Xilinx VHDL language development environment serial interface design
digital_lock
- Verilog code for digital combinational lock //BCAC – Unlock sequence //wrong sequence –alaram goes on and goes off only after pressin another 4 wrong buttons. //once the lock is open ,we can close the lock by pressin any key //From any state
daima
- 用VHDL语言设计一个8位加法器： 在八位加法器代码一中：加法器是由两个4位二进制加法器U1和U2组成的8位加法器逻辑电路，其中U1用来装载8位加法器中两个加数的低4位，而U2则用来装载高4位。在设计4位加法器时，定义输入信号量CIN、A、B以及输出信号量S、Cout。定义信号量SINT/AA/BB，将加数A和0并置后赋给AA，加数B和0并置后赋给BB，形成5位二进制数，这是为在做加法时发生溢出所做的处理，然后将加数AA与BB以及进位Cin相加赋给SINT，并将SINT的低4位赋给加数和S输
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- 基于FPGA的数字频率计-FPGA-based digital frequency meter
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- 洗衣机控制vhdl，洗涤、漂洗和脱水，每个功能持续的时间分别为20秒、15秒和10秒-vhdl
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- 簡易的七段猜數字，先設定所猜數字後，按下a鍵輸入，開始猜數字，每輸入兩數字後，按下a鍵確認，更新上下限。-Simple seven-segment number guessing, first set the number guessing, and then press a key to enter the start number guessing, each of the two digital input, press a button to confirm, update the up
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- 4*4键盘输入，1602显示，可修改密码的电子密码锁。-4* 4 keyboard input, the 1602 display, electronic locks to change your password.
urunn_length_s
- <p>用verilog 开发应用于图像压缩编码中使用行程长度编码(run lengthencoding，RLE)对交流系数(Aa)进行编码。</p> -<p> With verilog development for image compression using run length encoding (run lengthencoding, RLE) coding to encode the exchange coefficient (Aa). <
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- 本程序是用Xilinx ISE 软件编写的。它完成了（7,3）码的编码工作。里面有源程序和用于仿真的测试文件-The program is written using the Xilinx ISE software. (7,3) code encoding. Inside source for simulation test file
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- Controller for the ADC on the PmodAD1
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- 这个程序就是序列检测器的vhdl实现，真麻烦啊-This program is the sequence detector vhdl achieve real trouble