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fftmatlab
- fft在dspbuilder下产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过-fft in dspbuilder under VHDL source code and test incentives document matl ab model, the simulation under through modelsim
ddsmatlab
- dds在dspbuilder下产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过-dds dspbuilder under the VHDL source code and test incentives document matl ab model, the simulation under through modelsim
mxuliematlab
- m序列在dspbuilder下产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过-m sequence in dspbuilder under VHDL source code and test incentives document matl ab model, the simulation under through modelsim
sinmdlmatlab
- 正弦波在dspbuilder下产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过-sine wave in dspbuilder under VHDL source code and test incentives document matl ab model, the simulation under through modelsim
s3esk_rotary_encoder_interface
- Xilix spartan 3E 旋转编码器接口,脉冲方向识别,AB脉冲滤波 Rotary Encoder Interface Demonstrates how to use the rotary encoder portion of the rotary pushbutton switch.-Xilix spartan 3E rotary encoder interface, pulse direction identification, AB pulse filter Ro
comp
- 用VHDL设计实现3位二进制比较器，其中AB为两个数值输入端口，YAYBYCW为比较结果-VHDL Design and Implementation with 3-bit binary comparator which AB values for the two input ports, YAYBYCW to compare the results
rotW
- Rotating Wheel is a simple digital circuit which makes use of a Seven Segment Display (SSD). It causes a continuous clockwise/anticlockwise movement of the SSD segments. Also, the circulatory movements are made more realistic by providing momentary o
application-in-card-and-servo-drive
- AB相编码器解码接口_PWM输出SOPC方案及其在运动控制卡和伺服驱动器中的应用-AB phase encoder decoder interface _PWM output SOPC program and its application in motion control card and servo drive
AB-4F
- 基于CPLD 的四倍频辩向电路设计-24位计数 8位单片机数据输出-Based on the CPLD optical pulse encoder signal multiplier circuit design
lock
- 1、列出真值表，画出卡诺图，写出逻辑表达式。 2、只有按下AB、BD、AD时，锁才打开，其余的都不能开锁。 3、还必须有一个报警系统，有警为1，无警为0。 4、最后用Protues进行仿真。 -1 lists the truth table, draw the Karnaugh map, write a logical expression. 2, only press the AB, BD, AD, lock open, and the rest can not unlock.
motor
- 状态机电路，驱动步进马达的四相控制线圈A、B、C、D。马达向前 的四相控制线圈通电过程为：A-AB-B-BC-C-CD-D-DA-A…,后退的过程为A-DA-D-DC -C-BC-B-AB-A…,输入时钟信号CLK和DIR方向控制端控制马达的前进和后退。 -The state machine circuit, the driving of the stepping motor, the four-phase control coils A, B, and C, and D. The mo
chengxu
- 读取外部RAM的状态机 RAM接口OE，输出使能 WR，低电平写RAM AB【7：0】地址总线 DB【7：0】地址总线 //将RAM 0至127的数据读出并相加最后的结果存入地址254（低8位）255（高8位） -State machine reads the external RAM RAM interface OE Output Enable WR, low-level to write RAM AB [7:0] address bus DB [7:0
daima
- Rst是低电平有效的系统复位信号，Clk是时钟信号。AB[5：0]是地址信号，DB[7：0]是数据信号，wr是低电平有效的写信号。start是启动信号。 模块中有一个64x8的双端口的存储器。系统复位结束后，可以通过AB、DB和wr信号向同步存储器写入数据。当写入64个数据后，给出一个Clk周期宽度的脉冲信号start，则系统从存储器0地址处开始读出数据，读出的8位数据从低位开始以3位为一组，每个时钟周期输出一组，即第一个时钟周期输出[2：0]位，第二个时钟周期输出[5：3]位，第三个周期
RAM_Delay
- 利用块RAM实现数据延时，ab两路数据的位宽都是32位，a路延时16个时钟，b路延时8个时钟-Using block RAM data latency, ab two way data bits wide is 32, a way to delay 16 clock, eight clock delay b road
ENC_ab_dir
- 产生相差90°的AB相脉冲，并且模拟AB相位的超前或滞后，用于ABZ编码器信号的分析(The AB phase pulse with a difference of 90 degrees is produced and the AB phase is simulated forward or lagging, for the analysis of the signal of the ABZ encoder)